Impact of Adaptive Voltage Scaling on Aging-Aware Signoff

Abstract

Abstract-Transistor aging due to bias temperature instability (BTI) is a major reliability concern in sub-32nm technology. Aging decreases performance of digital circuits over the entire IC lifetime. To compensate for aging, designs now typically apply adaptive voltage scaling (AVS) to mitigate performance degradation by elevating supply voltage. Varying the supply voltage of a circuit using AVS also causes the BTI degradation to vary over lifetime. This presents a new challenge for margin reduction in conventional signoff methodology, which characterizes timing libraries based on transistor models with pre-calculated BTI degradations for a given IC lifetime. Many works have separately addressed predictive models of BTI and the analysis of AVS, but there is no published work that considers BTI-aware signoff that accounts for the use of AVS during IC lifetime. This motivates us to study how the presence of AVS should affect aging-aware signoff. In this paper, we first simulate and analyze circuit performance degradation due to BTI in the presence of AVS. Based on our observations, we propose a ruleof-thumb for chip designers to characterize an aging-derated standardcell timing library that accounts for the impact of AVS. According to our experimental results, this aging-aware signoff approach avoids both overestimation and underestimation of aging -either of which results in power or area penalty -in AVS enabled systems.

On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling

“…The STA results show that these implementations of the flat margin method have no timing violation in Table VI, which validates our implementation approach. We use (4) where is the delay of a circuit without aging when .…”

“…We assume , 10 years DC BTI stress, and a targeted path (or cell) delay equal to 101% of the path (or cell) delay at . 4 After the AVS emulation, we calculate the after 10 years of DC BTI stress. The results in Table I imply the following: 1) When the cell chain is composed of a set of diverse cells (Row 13 in Table I) 5 the of the cell chain converges to a value similar to that of chains composed of single-type cells (i.e., 0.55 versus 0.53, 0.51, 0.62, 0.53, 0.56 from AND2, OR2, NOR2, NAND2 and XOR2 chains, respectively.…”

Methodology for Electromigration Signoff in the Presence of Adaptive Voltage Scaling

“…Adler et al [ [23] focus on the interactions between behaviors of AVS and BTl while ignoring EM degradation. Recently, Chan et al [8] study sign off strategies that consider interactions between AVS and BTl, but do not consider EM in their work.…”

“…Our work falls at the intersection of categories (b) and (c), building on that of [8]. We consider EM signoff strategies in the presence of BTl and AVS, and we investigate approaches to the design of EM-durable circuits.…”

“…To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. voltage scaling (AVS) [8]. To meet lifetime requirements, design teams overcome mean time to failure (MTTF) with respect to EM-induced interconnect voids and shorts by applying design guardbands [19] [l3] [24] [21].…”