Atomically Controlled Processing for Group IV Semiconductors by Chemical Vapor Deposition

Murota, Junichi; Sakuraba, Masao; Tillack, Bernd

doi:10.1143/jjap.45.6767

Cited by 112 publications

(159 citation statements)

References 87 publications

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“…Although the PH 3 partial pressure in this work is higher than in their case, the P dose in Refs. [4,5,11] is about 2 ~ 3 times higher than in our case. These results strongly suggest that the amount of P dose is influenced by the partial pressure of H 2 .…”

Section: Ecs Transactions 16 (10) 495-502 (2008)contrasting

confidence: 64%

Vapor Phase Doping with N-type Dopant into Silicon by Atmospheric Pressure Chemical Vapor Deposition

Takeuchi¹,

Nguyen²,

Leys³

et al. 2008

ECS Trans.

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Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses tend to saturate at about 0.8 and 1.0 monolayer of Si, respectively. Therefore, these processes are self-limited in both cases. When a Si cap layer is grown on the P-covered Si(001), high P concentration of 3.7 × 10 20 cm -3 at the heterointerface in the Sicap/P/Si-substrate layer stacks is achieved. Due to As desorption and segregation toward the Si surface during the temperature ramp up and during the Si-cap growth, the As concentration at the heterointerface in the Si-cap/As/Si-substrate layer stacks was lower compared to the P case. These results allowed us to evaluate the feasibility of the VPD process to fabricate precisely controlled doping profiles.

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Section: Ecs Transactions 16 (10) 495-502 (2008)contrasting

confidence: 64%

Vapor Phase Doping with N-type Dopant into Silicon by Atmospheric Pressure Chemical Vapor Deposition

Takeuchi¹,

Nguyen²,

Leys³

et al. 2008

ECS Trans.

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“…These devices were fabricated using a high-quality low-temperature epitaxially grown heterostructure incorporating a Si buffer layer, a strained SiGe layer and a Si capping layer. The heterostructure was grown in an ultraclean low-pressure chemical vapour deposition (CVD) system [12]. The deposition temperature was 750 °C for the Si buffer layer (100 nm thick), 500 °C for the strained SiGe layer (7 nm thick), and 500 °C for the Si capping layer (10 nm thick).…”

Section: Methodsmentioning

confidence: 99%

Capture/Emission Processes of Carriers in Heterointerface Traps Observed in the Transient Charge-Pumping Characteristics of SiGe/Si-Hetero-Channel pMOSFETs

Tsuchiya

Yoshida

Sakuraba

et al. 2011

KEM

Self Cite

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Abstract. Transient phenomena related to carrier capture/emission processes in interface traps were observed in the the charge pumping (CP) characteristics of SiGe/Si hetero-channel pMOSFETs, i.e., the CP characteristics were found to depend on the on/off time of the gate pulse. From these observations, time constants for the processes both in SiGe/Si heterointerface traps and in gate-oxide interface traps were derived. The time constant is considered to depend on the energy level of the interface traps that are present over a wide range within the energy gap. Therefore, these phenomena provide an interesting way of evaluating the discrete energy levels of interface traps in nanometer-scale devices containing only a few traps.

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“…1 shows the sheet resistance after 3 LA scans as function of exposure time to the precursor gas. Since the incorporated boron dose increases with time [3,9], the amount of B atoms that can be activated also increases, leading to lower Rs. A minimal value does however exist, due to the incorporated concentration limit set by the temperature-dependent solid solubility of the dopant.…”

Section: Methodsmentioning

confidence: 99%

Use of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology

et al. 2010

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We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 °C, we measured an active dopant concentration of about 2.1 × 10 20 cm -3 and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1-4 × 10 13 cm -2 ) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values.

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Atomically Controlled Processing for Group IV Semiconductors by Chemical Vapor Deposition

Cited by 112 publications

References 87 publications

Vapor Phase Doping with N-type Dopant into Silicon by Atmospheric Pressure Chemical Vapor Deposition

Vapor Phase Doping with N-type Dopant into Silicon by Atmospheric Pressure Chemical Vapor Deposition

Capture/Emission Processes of Carriers in Heterointerface Traps Observed in the Transient Charge-Pumping Characteristics of SiGe/Si-Hetero-Channel pMOSFETs

Use of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology

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