Assertion-Based Design

Foster, Harry; Krolnik, Adam; Lacey, David

doi:10.1007/978-1-4419-9228-4

Cited by 158 publications

(52 citation statements)

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“…To Coss-trigger Matrix Verification (ABV) has become one of the most important and efficient RTL verification techniques, and has gained a lot of attention in industry for pre-silicon verification [2].…”

Section: En Enmentioning

confidence: 99%

“…Post-silicon validation involves three major activities: (1) detecting errors through embedded DfD (Design-for-Debug) infrastructures by means of applying a proper stimulus, (2) localizing and identifying the root cause of problems, (3) correcting or bypassing errors. The post-silicon bug localization step involves identifying the location-time pair of bugs and is the most time-consuming step.…”

Section: Introductionmentioning

confidence: 99%

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An infrastructure for debug using clusters of assertion-checkers

Neishaburi

Žilić

2012

Microelectronics Reliability

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Section: En Enmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An infrastructure for debug using clusters of assertion-checkers

Neishaburi

Žilić

2012

Microelectronics Reliability

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“…They also provided a form of functional coverage [6] as well as the checking results. These messages give an indication of the effect of the testcase and help to analyze the quality of random simulations.…”

Section: Assertion Based Checkersmentioning

confidence: 99%

Design of SoC verification platform based on VMM methodology

Kong

Yong

et al. 2009

2009 IEEE 8th International Conference on ASIC

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A VMM-based verification platform has been implemented and applied to Yak SoC in this paper. The whole verification environment uses the System Verilog language, and the simulation tool adopted is Synopsys VCS-MX200606. The verification IP and System Verilog assertions help to heighten the performance of the platform. The verification results indicate that design errors oftiming and anti-protocols have been exactly checked out with 100% verification coverage. The proposed platform, possessing fine configurability, flexibility and high performance, can be reused in similar verifications ofother design].

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“…Nowadays, significant resources are devoted towards verification, which can consume up to 70% of the development time in order to meet tight time-to-market deadlines [1]. Simulation is still a predominant method for verifying the functional correctness of digital designs due to its ability to scale with large circuits; however, the effectiveness of this approach is entirely dependent on the quality of the test vectors used.…”

Section: Introductionmentioning

confidence: 99%

Mu-GSIM: A mutation testing simulator on GPUs

Tong

Boulé

Žilić

2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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Graphics Processing Units (GPUs) have recently gained widespread usage as an advanced parallel platform for accelerating compute intensive applications. The maturity of programming interfaces and the improved programmability of GPUs have enabled the development of parallel algorithms that leverage the wealth of compute power provided by them. In this paper, we present µ-GSIM, a GPU-based simulation tool that leverages the inherent bit parallelism of GPUs for accelerating simulations of mutated digital circuits. We propose an efficient mapping of multiple mutated circuits on the GPU's device memory, where we exploit as much data parallelism as possible so our GPU simulation kernel can achieve maximal performance by operating on independent data. Results show that with the largest ITC'99 circuit benchmarks we were able to achieve a 60% decrease in memory usage while gaining a 5.4× increase in simulation performance. Additionally, we demonstrated a speedup of at least 95× against a commercial event-driven simulation tool running on a conventional processor. This is beneficial in the quest for improving test quality.

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Assertion-Based Design

Cited by 158 publications

References 0 publications

An infrastructure for debug using clusters of assertion-checkers

An infrastructure for debug using clusters of assertion-checkers

Design of SoC verification platform based on VMM methodology

Mu-GSIM: A mutation testing simulator on GPUs

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