Design of SoC verification platform based on VMM methodology

Kong, Lu; Wu, Wuchen; Yong, He; He, Ming; Zhou, Zhenghu

doi:10.1109/asicon.2009.5351223

Cited by 3 publications

(2 citation statements)

References 5 publications

(2 reference statements)

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“…The occurrence of these requirements makes a big increase in verification workload. In current SoC design flows, verification is becoming a bottleneck of the entire design flow [1]. As the traditional verification method can not meet the requirements of the design, a new verification approach is needed.…”

Section: Introductionmentioning

confidence: 99%

An Advanced Verification Platform Based on UVM

Wang

2014

AMM

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An advanced verification platfrom based on UVM architecture is implemented in this paper. This paper presents a hierarchical verification environment that is portable, reusable, and easy to extend, which is constructed based on an object oriented language named System Verilog. The verification platform is applied to verify a RFID (Radio Frequency Identification) tag chip which is compliant with the ISO/IEC15693 standard, communicates with a reader outside through a RF analog circuitry, completes anti-collision flow, selects card, authenticates based on SM7 algorithm and controls the writing and reading of EEPROM inside. According to the instruction supported by the tag chip is wide and variety, and further more it’s very rich in the command frame contents, the advanced verification platform which achieves the constraint-random stimulus generation, functional coverage and self-check mechanism, reduces the verification cycle, improves verification efficiency and ensures verification adequacy.

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Section: Introductionmentioning

confidence: 99%

An Advanced Verification Platform Based on UVM

Wang

2014

AMM

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“…Enhancing reusability has become a significant means of shortening the time, improving the accuracy, and reducing the costs of verification. Reusability at the code level has been maturely supported, such as by the verification methodology manual (VMM) [6,7] and universal verification methodology (UVM) [8]. On the other hand, verification intellectual property (VIP) is efficiently applied in standard interface verification.…”

Section: Introductionmentioning

confidence: 99%

A novel intelligent verification platform based on a structured analysis model

Xie¹,

Wang²,

Lian³

et al. 2013

Sci. China Inf. Sci.

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Intelligent control based on intelligent characteristic model and its application Science in China Series F-Information Sciences 46, 225 (2003); Design and verification of intelligent multi-model adaptive control system of Tiangong-1 based on control moment gyros SCIENTIA SINICA Technologica 44, 131 (2014); Finite Verification for Robustness of Discrete Systems Under Structured Perturbations Chinese Science Bulletin 39, 886 (1994); Swarm robotics platform for intelligent interaction Virtual Reality & Intelligent Hardware 1, 316 (2019); Model based verification of dynamically evolvable service oriented systems SCIENCE CHINA Information Sciences 59, 032101 (2016);. RESEARCH PAPER. SCIENCE CHINA Information Sciences

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A method to make SoC verification independent of pin multiplexing change

Ghosh¹,

Hira²,

Garg³

2013

2013 International Conference on Computer Communication and Informatics

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As the size and complexity of System-On-Chip (SoC) design is increasing rapidly, a portable and structured verification (testbench) environment is desired to cope with time to market. The pin multiplexing complexity i.e number of functions/peripherals (IPs) multiplexed on a single I/O pad is growing rapidly as many functions/IPs are getting integrated into single device. There are SoCs where four or more functions/peripherals are multiplexed on a single chip pad as the application usage of each IP/function is mutually exclusive in nature. This pin multiplexing option changes across SoCs and also in between different releases for the same SoC. Over time, it is being observed that this I/O pad multiplexing becomes major bottleneck in reusing/porting/creating testbench and verification environment across SoCs and releases. In this paper, we are proposing a new testbench layer (i.e "Function mapping") in between the device under verification(DUV) and the various testbench components (e.g testbench drivers/ testbench monitors/bus functional models). This new layer reduces the overall verification cycle time significantly (approx 20% to 50%). We will discuss this layer implementation and usage in detail and results of the proposed approach.

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Design of SoC verification platform based on VMM methodology

Cited by 3 publications

References 5 publications

An Advanced Verification Platform Based on UVM

An Advanced Verification Platform Based on UVM

A novel intelligent verification platform based on a structured analysis model

A method to make SoC verification independent of pin multiplexing change

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