Arsenic decapping and half cycle reactions during atomic layer deposition of Al2O3 on In0.53Ga0.47As(001)

Shin, Byoungchul; Clemens, Jonathon B.; Kelly, Michael A.; Kummel, Andrew C.; McIntyre, Paul C.

doi:10.1063/1.3452336

Cited by 38 publications

(29 citation statements)

References 13 publications

(7 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The TMA pre-treatment prior to the high-k deposition on III-V channel materials has been widely employed and proven to eliminate native oxide on III-V surface. 16,17 MOSCAPs were fabricated by evaporation of Pd gate metal and Ti/Au backside ohmic contact, followed by annealing in forming gas (FG) ambient. TEM (transmission electron microscopy), EDX (energy dispersive X-ray spectroscopy), and XPS were used to investigate the physical and chemical structure of the high-k/III-V interface.…”

Section: Methodsmentioning

confidence: 99%

High-k dielectrics on (100) and (110) n-InAs: Physical and electrical characterizations

Wang

Doornbos²,

Astromskas³

et al. 2014

AIP Advances

View full text Add to dashboard Cite

Two high-k dielectric materials (Al2O3 and HfO2) were deposited on n-type (100) and (110) InAs surface orientations to investigate physical properties of the oxide/semiconductor interfaces and the interface trap density (Dit). X-ray photoelectron spectroscopy analyses (XPS) for native oxides of (100) and (110) as-grown n-InAs epi wafers show an increase in As-oxide on the (100) surface and an increase in InOx on the (110) surface. In addition, XPS analyses of high-k (Al2O3 and HfO2) on n-InAs epi show that the intrinsic native oxide difference between (100) and (110) epi surfaces were eliminated by applying conventional in-situ pre-treatment (TriMethyAluminium (TMA)) before the high-k deposition. The capacitance-voltage (C-V) characterization of HfO2 and Al2O3 MOSCAPs on both types of n-InAs surfaces shows very similar C-V curves. The interface trap density (Dit) profiles show Dit minima of 6.1 × 1012/6.5 × 1012 and 6.6 × 1012/7.3 × 1012 cm−2 eV−1 for Al2O3 and HfO2, respectively for (100) and (110) InAs surfaces. The similar interface trap density (Dit) on (100) and (110) surface orientation were observed, which is beneficial to future InAs FinFET device with both (100) and (110) surface channel orientations present.

show abstract

Section: Methodsmentioning

confidence: 99%

High-k dielectrics on (100) and (110) n-InAs: Physical and electrical characterizations

Wang

Doornbos²,

Astromskas³

et al. 2014

AIP Advances

View full text Add to dashboard Cite

show abstract

“…5,9 The key feature of the bilayer capacitors, which is different from single layer dielectrics, is that the maximum accumulation capacitance density of bilayer gate oxide increases from 1.5 lF/cm 2 to 2.0 lF/cm 2 after FGA, whereas no such effect of FGA has been observed for the single layer Al 2 O 3 MOSCAPs investigated. 10 The leakage current density across the bilayer gate dielectrics was also compared to that of Al 2 O 3 single layers. Figure 2 plots the gate leakage current density measured at flatband voltage as a function of the capacitance-derived equivalent SiO 2 thickness (CET).…”

mentioning

confidence: 99%

Titania/alumina bilayer gate insulators for InGaAs metal-oxide-semiconductor devices

Ahn

Geppert

Gunji

et al. 2011

Applied Physics Letters

Self Cite

View full text Add to dashboard Cite

We describe the electrical properties of atomic layer deposited TiO2/Al2O3 bilayer gate oxides which simultaneously achieve high gate capacitance density and low gate leakage current density. Crystallization of the initially amorphous TiO2 film contributes to a significant accumulation capacitance increase (∼33%) observed after a forming gas anneal at 400 °C. The bilayer dielectrics reduce gate leakage current density by approximately one order of magnitude at flatband compared to Al2O3 single layer of comparable capacitance equivalent thickness. The conduction band offset of TiO2 relative to InGaAs is 0.6 eV, contributing to the ability of the stacked dielectric to suppress gate leakage conduction.

show abstract

“…The fabrication procedure has been thoroughly tuned throughout the years, and further details about the process have been widely reported in our previous papers. 21, [25][26][27]38 Along this work and for clarity purposes, reference samples that underwent As 2 decapping and FGA are identified by the code FGA-#1, while those annealed in O 2 are assigned the code O2A-#2. Samples that were intentionally air-exposed are identified with the code AE: the set of samples that underwent FGA is identified as AE+FGA-#3 and those that were not annealed are assigned the identifier AE-#4.…”

Section: Methodsmentioning

confidence: 99%

Lack of correlation between C-V hysteresis and capacitance frequency dispersion in accumulation of metal gate/high-k/n-InGaAs metal-oxide-semiconductor stacks

Pazos

Aguirre

Tang

et al. 2018

Journal of Applied Physics

View full text Add to dashboard Cite

The correlation between capacitance-voltage hysteresis and accumulation capacitance frequency dispersion of metal gate/high-k/n-InGaAs metal-oxide-semiconductor stacks is experimentally assessed. Samples fabricated employing forming gas annealing (FGA) or substrate air exposure to obtain different densities of defects were thoroughly characterized and the results were compared with previous literature on the topic. Results indicate a lack of correlation between capacitancevoltage hysteresis and accumulation capacitance dispersion with frequency, suggesting that defects with remarkably different kinetics are involved in each phenomenon. This is assessed through the dependence of the capacitance-voltage hysteresis with DC bias and stress time, observing that permanent interface defect depassivation under bias has no effect on the hysteresis width after stress. Overall, capacitance-voltage hysteresis probes slow trapping mechanisms throughout the oxide and the bandgap, which are consistent with the negative charge trapping characteristic of the currenttime curves for FGA samples at constant voltage stress. Instead, accumulation capacitance frequency dispersion probes defects with short trapping/detrapping characteristic times that can be linked to the stress induced leakage current of air exposed samples under constant DC stress. Experimental results indicate that each effect must be assessed separately due to the large difference in the kinetics of the probed defects.

show abstract

Arsenic decapping and half cycle reactions during atomic layer deposition of Al2O3 on In0.53Ga0.47As(001)

Abstract: Articles you may be interested inSynchrotron radiation photoemission study of interfacial electronic structure of HfO2 on In0.53Ga0.47As(001)-4×2 from atomic layer deposition Appl. Phys. Lett.

Cited by 38 publications

References 13 publications

High-k dielectrics on (100) and (110) n-InAs: Physical and electrical characterizations

High-k dielectrics on (100) and (110) n-InAs: Physical and electrical characterizations

Titania/alumina bilayer gate insulators for InGaAs metal-oxide-semiconductor devices

Lack of correlation between C-V hysteresis and capacitance frequency dispersion in accumulation of metal gate/high-k/n-InGaAs metal-oxide-semiconductor stacks

Contact Info

Product

Resources

About