Thin dielectric films are essential components of most micro-and nanoelectronic devices, and they have played a key role in the huge development that the semiconductor industry has experienced during the last 50 years. Guaranteeing the reliability of thin dielectric films has become more challenging, in light of strong demand from the market for improved performance in electronic devices. The degradation and breakdown of thin dielectrics under normal device operation has an enormous technological importance and thus it is widely investigated in traditional dielectrics (e.g., SiO 2 , HfO 2 , and Al 2 O 3 ), and it should be further investigated in novel dielectric materials that might be used in future devices (e.g., layered dielectrics). Understanding not only the physical phenomena behind dielectric breakdown but also its statistics is crucial to ensure the reliability of modern and future electronic devices, and it can also be cleverly used for other applications, such as the fabrication of new-concept resistive switching devices (e.g., nonvolatile memories and electronic synapses). Here, the fundamentals of the dielectric breakdown phenomenon in traditional and future thin dielectrics are revised. The physical phenomena that trigger the onset, structural damage, breakdown statistics, device reliability, technological implications, and perspectives are described.

Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >106 cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products.

Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2–Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D–CMOS hybrid microchips for memristive applications—CMOS stands for complementary metal–oxide–semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

We investigate the use and performance of the quasi-static memdiode model (QMM) when incorporated into large cross-point arrays intended for pattern classification tasks. Following Chua's memristive devices theory, the QMM comprises two equations, one equation for the electron transport based on the doublediode circuit with single series resistance and a second equation for the internal memory state of the device based on the so-called logistic hysteron or memory map. Ex-situ trained memdiodes with different MNISTlike databases are used to establish the synaptic weights linking the top and bottom wire networks. The role played by the memdiode electrical parameters, wire resistance and capacitance values, image pixelation, connection schemes, signal-to-noise ratio and device-to-device variability in the classification effectiveness are investigated. The confusion matrix is used to benchmark the system performance metrics. We show that the simplicity, accuracy and robustness of the memdiode model makes it a suitable candidate for the realistic simulation of large-scale neural networks with non-idealities.