In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during which the gate leakage increases above acceptable levels. In conditions of intrinsic BD, the leakage increase is due to the growth of damage within the oxide in localized regions. Observations concerning this damage are reviewed and discussed. The measurement of the current, voltage, and power dissipated during the BD transient are also reported and discussed in comparison with the data of structural damage. We then describe the current understanding concerning the dependence of the BD current transient on the conditions of electric field and voltage. In particular, as the oxide thickness and, as a consequence, the voltage levels used for accelerated reliability tests have decreased, the BD transient exhibits a marked change in behavior. As the stress voltage is decreased below a threshold value, the BD transient becomes slower. This recently discovered phenomenon has been termed progressive BD, i.e., a gradual growth of the BD spot and of the gate leakage, with a time scale that under operation conditions can be a large fraction of the total time to BD. We review the literature on this phenomenon, describing the current understanding concerning the dependence of the effect on voltage, temperature, oxide thickness, sample geometry, and its physical structure. We also discuss the possible relation to the so-called soft oxide BD mode and propose a simpler, more consistent terminology to describe different BD regimes. The last part of the paper is dedicated to exploratory studies, still at the early stages given the very recent subject, concerning the impact on the BD of materials for the metal-oxide-semiconductor gate stack and, in particular, metal gates.

Thin dielectric films are essential components of most micro-and nanoelectronic devices, and they have played a key role in the huge development that the semiconductor industry has experienced during the last 50 years. Guaranteeing the reliability of thin dielectric films has become more challenging, in light of strong demand from the market for improved performance in electronic devices. The degradation and breakdown of thin dielectrics under normal device operation has an enormous technological importance and thus it is widely investigated in traditional dielectrics (e.g., SiO 2 , HfO 2 , and Al 2 O 3 ), and it should be further investigated in novel dielectric materials that might be used in future devices (e.g., layered dielectrics). Understanding not only the physical phenomena behind dielectric breakdown but also its statistics is crucial to ensure the reliability of modern and future electronic devices, and it can also be cleverly used for other applications, such as the fabrication of new-concept resistive switching devices (e.g., nonvolatile memories and electronic synapses). Here, the fundamentals of the dielectric breakdown phenomenon in traditional and future thin dielectrics are revised. The physical phenomena that trigger the onset, structural damage, breakdown statistics, device reliability, technological implications, and perspectives are described.

Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >106 cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products.