Architecture of an HDTV Intraframe Predictor for a H.264 Decoder

Abstract

Multimedia applications need larger and larger bandwidth. The only way to face these demands is to provide more efficient compression algorithms, with the expense of computational complexity. The most efficient compression standard available today is the H.264/AVC. On the architectural point of view, an H.264 decoder can be seen as a system of six main modules: entropy decoder, inverse quantization, inverse transform, motion compensation, intraframe prediction and deblocking filter. These modules can be designed independently and enclosed in IPs, which could be used later to build an H.264 SoC. This paper presents an architecture design of intraframe prediction module. The system was completely built in VHDL language and prototyped over a Xilinx Virtex II Pro FPGA of 27,392 logic elements. The proposed architecture attained the required performance to decode HDTV video stream in realtime, i.e. 1920x1080 pixels at 30 frames per second, and used just 20% of the chip.

Area optimized H.264 Intra prediction architecture for 1080p HD resolution

“…From Table 2, the proposed design noted 21% increase in throughput while using only 48% of LUT resources as reported by [5]. The design in [7] supports 1080p HD at 30 fps using 7K LUT resources, three times more than used by our design.…”

“…The paper decodes 640x480 resolution H.264 video at 27 fps. Architecture in [5] utilizes separate local memory for storage, causing inefficient usage of on-chip memory. It does not reuse similar functional blocks.…”

“…The area comparison of Intra Prediction block with [5] is listed in Table 1 Our proposed architecture of intra prediction block achieves throughput of 64 fps for 1080HD resolution, including memory access latency. From Table 2, the proposed design noted 21% increase in throughput while using only 48% of LUT resources as reported by [5].…”

Design of High-Performance Intra Prediction Circuit for H.264 Video Decoder

“…The base architecture of our intra prediction circuit is the one described in [2]. As illustrated in Fig.…”

“…2 (a). We further investigated each prediction mode and found that some of the computations can be expressed by the following simpler equation: We propose to use another common computation unit to implement the function described by Equation (2). As shown in Fig.…”