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High performance video standards use prediction techniques to achieve high picture quality at low bit rates. The type of prediction decides the bit rates and the image quality. Intra Prediction achieves high video quality with significant reduction in bit rate. This paper present an area optimized architecture for Intra prediction, for H.264 decoding at HDTV resolution with a target of achieving 60 fps. The architecture was validated on Virtex-5 FPGA based platform. The architecture achieves a frame rate of 64 fps. The architecture is based on multi-level memory hierarchy to reduce latency and ensure optimum resources utilization. It removes redundancy by reusing same functional blocks across different modes. The proposed architecture uses only 13% of the total LUTs available on the Xilinx FPGA XC5VLX50T.

No abstract

High performance video standar techniques to achieve high picture quality at type of prediction decides the bit rates and t Intra Prediction achieves high video quality reduction in bitrate. This paper presents nov architecture for Intra prediction of H.264 de resolution. The architecture has been valid Virtex-5 FPGA based platform and achieved a fps. The architecture is based on multi-level m to reduce latency and ensure optimum resour removes redundancy by reusing same functio different modes. The proposed architecture the total LUTs available on the Xilinx FPGA X