Design of High-Performance Intra Prediction Circuit for H.264 Video Decoder

Abstract

Abstract-This paper proposes a high-performance architecture of the H.264 intra prediction circuit. The proposed architecture uses the 4-input and 2-input common computation units and common registers for fast and efficient prediction operations. It avoids excessive power consumption by the efficient control of the external and internal memories. The implemented circuit based on the proposed architecture can process more than 60 HD (1,920x1,088) image frames per second at the maximum operating frequency of 101 MHz by using 130 nm standard cell library.