Application-related characterization and theoretical potential of wide-bandgap devices

Endruschat, Achim; Heckel, Thomas; Gerstner, Holger; Joffe, Christopher; Eckardt, Bernd; März, Martin

doi:10.1109/wipda.2017.8170529

Cited by 6 publications

(4 citation statements)

References 5 publications

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“…Refs. [24,35] and Fig. 4 show that the minimum hardswitching losses occur while switching zero current and arise due to the capacitive switching losses (see Fig.…”

Section: Zero-current Switching -Minimum Hard-switching Lossesmentioning

confidence: 99%

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New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

Anderson

Zulauf

Kolar

et al. 2020

IEEE Open J. Power Electron.

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Figures-of-merit (FOMs) are widely-used to compare power semiconductor materials and devices and to motivate research and development of new technology nodes. These material-and device-specific FOMs, however, fail to directly translate into quantifiable performance in a specific power electronics application. Here, we combine device performance with specific bridge-leg topologies to propose the extended FOM, or X-FOM, a figure-of-merit that quantifies bridge-leg performance in multi-level (ML) topologies and supports the quantitative comparison and optimization of topologies and power devices. To arrive at the proposed X-FOM, we revisit the fundamental scaling laws of the on-state resistance and output capacitance of power semiconductors to first propose a revised device-level semiconductor Figure-of-Merit (D-FOM). The D-FOM is then generalized to a multi-level topology with an arbitrary number of levels, output power, and input voltage, resulting in the X-FOM that quantitatively compares hard-switched semiconductor stage losses and filter stage requirements across different bridgeleg structures and numbers of levels, identifies the maximum achievable efficiency of the semiconductor stage, and determines the loss-optimal combination of semiconductor die area and switching frequency. To validate the new X-FOM and showcase its utility, we perform a case study on candidate bridge-leg structures for a three-phase 10 kW photovoltaic (PV) inverter, with the X-FOM showing that (a) the minimum hard-switching losses are an accurate approximation to predict the theoretically maximum achievable efficiency and relative performance between bridge-legs and (b) the 3-level bridge-leg outperforms the 2-level configuration, despite utilizing a SiC MOSFET with a lower D-FOM than in the 2-level case.

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“…Refs. [24,35] and Fig. 4 show that the minimum hardswitching losses occur while switching zero current and arise due to the capacitive switching losses (see Fig.…”

Section: Zero-current Switching -Minimum Hard-switching Lossesmentioning

confidence: 99%

“…For a 2-level bridge-leg (like in Fig. 1b with N = 1) with a DC input voltage U dc , a filter inductor output current I rms , and a switching frequency f sw 2L , the losses in the bridge-leg can be calculated as [10,35]:…”

Section: Optimal Power Semiconductor Losses For Two-level Bridgementioning

confidence: 99%

New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

Anderson

Zulauf

Kolar

et al. 2020

IEEE Open J. Power Electron.

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“…To illustrate the relevance and limitations of each method to the topic of transistor characterization, the applicable measurements setups and the prevalent signal waveforms are depicted in figure 1. A fast TVS diode as DUT 2 shows pivotal effects: turn-on time in single nanosecond range with subsequent clamping of the voltage.…”

Section: Transmission Line Pulsingmentioning

confidence: 99%

“…Therefore, state of the art characterization includes different kinds of measurement setups for different sets of parameters. Ranging from pulsed techniques [2] to frequency-based methods [3][4][5] every technique needs different setups and operational requirements. The gold standard method that comes closest to the conditions the switches are exposed to in the field is the double pulse test (DPT).…”

Section: Introductionmentioning

confidence: 99%

Measuring Transient I/V Turn-On Behavior of a Power MOSFET without a Current Sensor

Helmut¹,

Groos²,

Wachutka³

et al. 2021

ISPS'21 Proceedings

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Double pulse test (DPT) is usually used to characterize and verify turn-on/turn-off operation of power switches. Yet, new high frequency switching devices based on SiC and GaN technologies require much more elaborate DPT circuitry and sensing nodes compared to the established Si devices. Especially, suitable current sensors are challenging to realize and always limit the bandwidth. We propose a Transmission Line Pulsing (TLP)-based technique, which we call sensor gap TLP (sgTLP) and which is capable to monitor the transient currents and voltages during the turn-on sequence of a power MOSFET, without the need of a current sensor. The proposed sgTLP approach is compared to established TLP methods in two applications: the passive switching of a fast transient voltage suppression diode and the active switching of a Si power MOSFET. The novel sgTLP shows the same or better characteristics than both of the standard methods, but needs only one measurement, where standard TLP would need two separate methods. Especially, sgTLP detected rise times of 54 ps of a current and 52 ps of a voltage signal using a pulse duration of 100 ns. The measured characteristics of the MOSFET turnon reveals several inductive and capacitive coupling mechanisms that are not analyzable by the established TLP methods but become visible applying sgTLP.

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A Universal SPICE Field-Effect Transistor Model Applied on SiC and GaN Transistors

Endruschat

Novak

Gerstner

et al. 2019

IEEE Trans. Power Electron.

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Application-related characterization and theoretical potential of wide-bandgap devices

Cited by 6 publications

References 5 publications

New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

Measuring Transient I/V Turn-On Behavior of a Power MOSFET without a Current Sensor

A Universal SPICE Field-Effect Transistor Model Applied on SiC and GaN Transistors

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