Analytical threshold voltage modeling of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs

Goel, Ekta; Singh, Balraj; Kumar, Sanjay; Singh, Kunal; Jit, Satyabrata

doi:10.1007/s12648-016-0918-6

Cited by 12 publications

(2 citation statements)

References 26 publications

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“…The performance of the proposed s‐Si GC‐DMDG MOSFET is compared with the previous works, as demonstrated in Table 1. It is observed from Table 1 that the proposed s‐Si GC‐DMDG device has lower I OFF , higher I ON / I OFF ratio, and lower SS compared to s‐Si GC‐DG device and Guassian doped s‐Si DMDG MOSFET with channel length 40 nm 21,35 . Besides, the proposed s‐Si GC‐DMDG MOSFET has higher I ON / I OFF ratio than DMG junction less MOSFET with channel length of 80 nm 36 .…”

Section: Resultsmentioning

confidence: 90%

“…It is observed from Table 1 that the proposed s-Si GC-DMDG device has lower I OFF , higher I ON /I OFF ratio, and lower SS compared to s-Si GC-DG device and Guassian doped s-Si DMDG MOSFET with channel length 40 nm. 21,35 Besides, the proposed s-Si GC-DMDG MOSFET has higher I ON /I OFF ratio than DMG junction less MOSFET with channel length of 80 nm. 36 Therefore, the proposed s-Si GC-DMDG MOSEFT has attained improved subthreshold characteristics using DMG structure with graded channel engineering.…”

Section: Resultsmentioning

confidence: 98%

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Analytical modeling of subthreshold current and swing of strained‐Si graded channel dual material double gate MOSFET with interface charges and analysis of circuit performance

Suddapalli

Nistala

2020

Int J Numerical Modelling

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In this paper, a two-dimensional (2-D) center channel potential based subthreshold current (SC) and subthreshold swing (SS) are developed analytically for strained-Si (s-Si) graded-channel dual-material double gate (GC-DMDG) MOSFET with interface charges. The proposed analytical model is extracted by solving 2-D Poisson equation in s-Si graded-channel using appropriate boundary conditions. The analytical 2-D model includes effects of various MOSFET parameters such as s-Si channel length, strain in the silicon substrate, and oxide interface charge density with damaged length by extensively analyzing channel potential, SC, and SS. Also, the subthreshold characteristics of the proposed s-Si GC-DMDG MOSFET demonstrate superior performance over s-Si graded channel double gate MOSFET. The numerical results obtained using TCAD of the proposed DG MOSFET are validated with the results attained from proposed analytical model. Moreover, the performance of CMOS inverter using s-Si GC-DMDG MOSFET is evaluated for different device parameters. It is investigated that the proposed s-Si GC-DMDG MOSFET has better noise margin than s-Si GC-DG MOSFET.

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Section: Resultsmentioning

confidence: 90%