Analytical Surface Potential Model with TCAD Simulation Verification for Evaluation of Surrounding Gate TFET

Abstract

-In this paper, a new two dimensional (2D) analytical modeling and simulation for a surrounding gate tunnel field effect transistor (TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunneling generation rate and thus we numerically extract the tunneling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

Optimization and performance indication of surrounding gate tunnel field‐effect transistors based on machine learning

“…Moreover, semiconductor industries experience an escalating growth in performance and complexity due to the steady downscaling of MOSFET technology that leads to many new novel nanostructures. However, the channel length reduction leads to the short channel effects (SCEs) and the exploration of new devices that use tunneling for their ON‐current 6–11 . The astounding property of the surrounding gate which offers excellent packing density has drawn attention among multigate architectures.…”

“…However, the channel length reduction leads to the short channel effects (SCEs) and the exploration of new devices that use tunneling for their ON-current. [6][7][8][9][10][11] The astounding property of the surrounding gate which offers excellent packing density has drawn attention among multigate architectures. SGTFETs exhibit enhanced gate control and superior resistance to unwanted SCEs and are widely analyzed as an effective candidate beyond the scaling limit of silicon.…”

Analytical Modelling and Simulation of Triple Material Quadruple Gate Tunnel Field Effect Transistors

“…In spite of the fact that TFET has these benefits, it experiences a low ON current (I ON ).So different methods to enhance the I ON of TFETs have been proposed [5][6]. This incorporates , various TFET gadget structures with different doors, for example, twofold, triple, all around entryway and so forth are being proposed and researched .In twofold door structure, two entryways control the channel, in triple door TFET the channel is controlled from three sides, and in all around door TFET channel is controlled from all around enhancing the electrostatic qualities over the traditional one [7][8][9]. As of late a potential advance has been presented by taking distinctive door material work (various material entryways) to the source closures and deplete end to diminish deplete control over channel enhancing numerous execution parameters, for example, deplete initiated boundary bringing down, HCEs and sub limit current conduction.…”

Analytical threshold voltage model for strained silicon GAA-TFET

“…[1][2][3] Therefore, tunnel field effect transistors (TFETs) have been considered as one of the most promising candidates for MOSFETs beyond 45 nm for future ultra-low power applications due to their better immunity to short channel effects, higher I ON /I OFF ratio, and so on. [4][5][6][7] However, TFETs to date show a low drain current due to the low band-to-band tunneling (BTBT) efficiency.…”