Analytical threshold voltage model for strained silicon GAA-TFET

A new T-shaped tunnel field-effect transistor (TTFET) with gate dielectric spacer (GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling (BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap (GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.

Section: Parameter Optimization For Gds-ttfetmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer

Han¹,

Zhang²,

Wang³

et al. 2019

“…[4] Multi-gate architectures such as fin field effect transistor (FinFET) and gate-all-around (GAA) greatly improve electrostatic control ability over the channel. [5] Among these new architectures, three-dimensional (3D) vertical devices provide a promising solution to overcome the bottleneck of semiconductor technology and improve the performance of traditional two-dimensional (2D) devices. The 3D vertical architecture devices have plenty advan-tages for future electronic.…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional vertical ZnO transistors with suspended top electrodes fabricated by focused ion beam technology

Sun

Hao

et al. 2022

Three-dimensional (3D) vertical architecture transistors represent an important technological pursuit, which have distinct advantages in device integration density, operation speed, and power consumption. However, the fabrication processes of such 3D devices are complex, especially in the interconnection of electrodes. In this paper, we present a novel method which combines suspended electrodes and focused ion beam (FIB) technology to greatly simplify the electrodes interconnection in 3D devices. Based on this method, we fabricate 3D vertical core-double shell structure transistors with ZnO channel and Al2O3 gate-oxide both grown by atomic layer deposition. Suspended top electrodes of vertical architecture could be directly connected to planar electrodes by FIB deposited Pt nanowires, which avoid cumbersome steps in the traditional 3D structure fabrication technology. Both single pillar and arrays devices show well behaved transfer characteristics with an I on/I off current ratio greater than 106 and a low threshold voltage around 0 V. The ON-current of the 2 × 2 pillars vertical channel transistor was 1.2 μA at the gate voltage of 3 V and drain voltage of 2 V, which can be also improved by increasing the number of pillars. Our method for fabricating vertical architecture transistors can be promising for device applications with high integration density and low power consumption.

“…Due to its band-to-band tunneling (BTBT) operation mechanism, the TFET is characterized as steep subthreshold swing at room temperature, low leakage current in off state and excellent short channel effects. [5,6] However, since a thin inversion layer on the surface of the channel of normal TFETs is necessary to exploit the gate-controlled BTBT between the channel and drain/source, the normal TFET is characterized as "point" tunneling device, resulting in the low on-state current and high threshold voltage, which are below the requirement set in ITRS [7] and are the main limitation of TFET. [8,9] To increase the on-state current, L-shaped channel TFET (LTFET), [10] U-shaped channel TFET (UTFET), [11,12] T-shaped gate TFET (TG-TFET), [13] Z-shaped TFET (ZS-TFET), [14] L-shaped gate TFET (LG-TFET), [10] elecronhole bilayer TFET (EHB TFET), [8] electro-statically doped source/drain double-gate tunnel field effect transistors (EDSDDG-TFETs), [15] L-shaped Ge source TFET (LS-TFET), [16] etc., are developed.…”

Section: Introductionmentioning

confidence: 99%

Simulation study of device physics and design of GeOI TFET with PNN structure and buried layer for high performance*

Wang¹,

Hu(胡晟)²,

Feng³

et al. 2020

Self Cite

Large threshold voltage and small on-state current are the main limitations of the normal tunneling field effect transistor (TFET). In this paper, a novel TFET with gate-controlled P+N+N+ structure based on partially depleted GeOI (PD-GeOI) substrate is proposed. With the buried P+-doped layer (BP layer) introduced under P+N+N+ structure, the proposed device behaves as a two-tunneling line device and can be shut off by the BP junction, resulting in a high on-state current and low threshold voltage. Simulation results show that the on-state current density I on of the proposed TFET can be as large as 3.4 × 10−4 A/μm, and the average subthreshold swing (SS) is 55 mV/decade. Moreover, both of I on and SS can be optimized by lengthening channel and buried P+ layer. The off-state current density of TTP TFET is 4.4 × 10−10 A/μm, and the threshold voltage is 0.13 V, showing better performance than normal germanium-based TFET. Furthermore, the physics and device design of this novel structure are explored in detail.