Optimization and performance indication of surrounding gate tunnel field‐effect transistors based on machine learning

Abstract

Selecting designs that efficiently optimize multiple objectives simultaneously is an important problem in several distinct industries. Typically, there is not a single ideal design; rather, there are several Pareto‐optimal designs that provide the best possible trade‐offs between the objectives. However, evaluating every design might be expensive, making a thorough search for the whole Pareto optimum set impractical. The aforementioned issue with technology computer‐aided design (TCAD) while investigating a multidimensional parameter set for device design is addressed using Pareto active learning (PAL) and the nondominated sorting genetic algorithm‐III (NSGA‐III) which are metaheuristics‐based multiobjective optimization (MOO) techniques. NSGA‐III adeptly analyzes the tradeoffs among multiple objectives while ensuring diversity in the design space. PAL forecasts the Pareto‐optimal set with intelligence by deliberately sampling the design space. This work focusses on improving the performance of surrounding gate tunnel field‐effect transistors (SGTFETs) by optimizing and assessing their complex designs in terms of multiple objectives, including power, energy, speed, and variability. This paper presents a novel MOO framework that incorporates machine learning (ML) approaches, including NSGA‐III and PAL in SGTFETs technology. The framework provides effective global optimization without gradients, allowing for the automatic recognition of the best solutions. The outcomes show the possibility of ML‐based MOO to create next‐generation nanoscale transistors.