Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling

Wang, Chao; Wu, Chunlei; Wang, Jiaxin; Huang, Qianqian; Huang, Ru

doi:10.1007/s11432-014-5196-3

Cited by 22 publications

(9 citation statements)

References 9 publications

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“…Instead of a full quantum treatment, the tunneling carriers are modeled by a generation-recombination process. For a given tunneling path of length L which starts at x = 0 and ends at x = L, holes are generated at x = 0 and electrons are generated at x = L [ 24 ]. Thus, the carrier tunneling rate can be equivalently processed by the generation rate and the tunnel current density of carriers tunneling from the source to the channel equals to electron charge times the integral of the generation rate G BTBT .…”

Section: Model Derivation For Inas/si Hsp-tfetmentioning

confidence: 99%

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Zhang

et al. 2019

Nanomaterials

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The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

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Section: Model Derivation For Inas/si Hsp-tfetmentioning

confidence: 99%

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Zhang

et al. 2019

Nanomaterials

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“…Furthermore, the source outer fringing capacitance is reduced with the increase of oxide thickness as described in (15). C gd is inversely proportional to the T OX as mentioned in (19) and (21) and it is clearly observed in Fig. 6b.…”

Section: Modelling Of Charge and Terminal Capacitancesmentioning

confidence: 70%

“…7a and b. As the N S increases, L 2 is increased [as given in (13)] which causes the reduction of C gd as indicated in (19) [22]. On the other hand, the C gs is increased with the increase of N S due to increase in depletion capacitance as verified from (17).…”

Section: Modelling Of Charge and Terminal Capacitancesmentioning

confidence: 86%

“…Double-gate TFETs [7], heterojunction TFETs [8], nanowire TFETs [9], gate all around TFETs [10,11], III-V TFETs [12], dual-metal-gate TFETs [13], gate-on-source only TFET [14] and L-shaped TFET [15] are some of the most key forms of TFETs. Many analytical models have been proposed until now to analyse the DC characteristics of TFETs [16][17][18][19]. The switching speed in circuits is strongly dependent on device capacitance, more specifically gate capacitance [20].…”

Section: Introductionmentioning

confidence: 99%

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Physics‐based capacitance model of Gate‐on‐Source/Channel SOI TFET

Mitra

Bhowmick

2018

Micro & Nano Letters

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A surface potential-based analytical capacitance model is proposed for gate-on-source-channel silicon on insulator (SOI) tunnel field effect transistor (GOSC TFET). The capacitance in the GOSC TFET is evidently shared by the gate-to-source capacitance which reduces the miller capacitance and leads to better switching speed in the circuit application. The effect of drain voltage, gate voltage, gate oxide thickness and source doping on the capacitance has been analysed in detail. The good matching between the modelled and Technology Computer-Aided Design (TCAD) simulated surface potential leads to the accurate calculation of capacitance. The validation of the capacitance model is done by comparing the model result with the simulation result and a good agreement between them validates the model formulation.

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“…According to Poisson equation, we can obtain the channel potential distribution function Φ(x, y) [13,14],…”

Section: Parameter Design Considerationmentioning

confidence: 99%

Electrical performance of static induction transistor with transverse structure

Liu

Wang

et al. 2016

Sci. China Inf. Sci.

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A novel static induction transistor with transverse surface gate structure was designed and successfully fabricated in this paper. Its basic electrical characteristics and frequency performance was investigated in depth. The optimum technological parameters such as source-gate space and epitaxial layer thickness for obtaining excellent frequency performance and high blocking voltage capacity were represented and discussed in detail. The main advantage of this work is that the performances of device were improved with simple structure and technological processes. The experimental and simulated results demonstrate the trans-conductance gm and gate-source breakdown voltage BV GS of the transverse type SIT increase from 60 to 87 ms and 20 to 26 V, respectively, in addition to obtaining higher than 100 MHz operating frequency under relatively simple technology processes compared with those of traditional vertical SIT.

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Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling

Cited by 22 publications

References 9 publications

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Physics‐based capacitance model of Gate‐on‐Source/Channel SOI TFET

Electrical performance of static induction transistor with transverse structure

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