Analytical and experimental methods for zero-temperature-coefficient biasing of MOS transistors

Shoucair, F.S.

doi:10.1049/el:19890802

Cited by 53 publications

(35 citation statements)

References 1 publication

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“…Temperature behavior is also shown in Fig. 3 where the well known ZT C points [11] are clearly manifested and follow the scaling trend of classical FD SOI [12]. Threshold voltage is extracted for these devices as a function of temperature.…”

Section: Scaling and High Temperature Behaviormentioning

confidence: 74%

DC and RF temperature behavior of deep submicron Graded Channel MOSFETs

Emam

Kumar

Ida

et al. 2009

2009 IEEE International SOI Conference

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The superior performance of Graded-Channel MOSFET over classical MOSFET transistors is demonstrated to extend to down scaled channel lengths. While keeping a normal down scaling trend, Graded-Channel devices continue to show favoured static and analog performances in comparison to classical devices. Graded-Channel devices are also characterized in high temperature and high frequency regimes of operation.

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Section: Scaling and High Temperature Behaviormentioning

confidence: 74%

DC and RF temperature behavior of deep submicron Graded Channel MOSFETs

Emam

Kumar

Ida

et al. 2009

2009 IEEE International SOI Conference

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“…A temperature-independent current bias circuit has been designed to provide constant current biasing to the adjustable delay controller circuit. Figure 5 shows the schematic of the temperature-independent current bias network developed using the zero-temperature coefficient (ZTC) [18] Since both positive and negative temperature coefficient resistors are available in the SOI process, temperature independent resistor can be implemented, thus constant bias voltages V P for the PMOS and V N for the NMOS transistors are generated. Figure 6 shows the schematic of the adjustable delay controller circuit with the temperature independent bias network.…”

Section: Temperature Independent Dead-time Controllermentioning

confidence: 99%

A UNIVERSAL SOI-BASED HIGH TEMPERATURE GATE DRIVER INTEGRATED CIRCUIT FOR SiC POWER SWITCHES WITH ON-CHIP SHORT CIRCUIT PROTECTION

Zuo

Islam

Huque

et al. 2011

Int. J. Hi. Spe. Ele. Syst.

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In recent years, increasing demand for hybrid electric vehicles (HEVs) has generated the need for reliable and low-cost high-temperature electronics which can operate at the high temperatures under the hood of these vehicles. A high-voltage and high temperature gate-driver integrated circuit for SiC FET switches with short circuit protection has been designed and implemented in a 0.8-micron silicon-on-insulator (SOI) high-voltage process. The prototype chip has been successfully tested up to 200ºC ambient temperature without any heat sink or cooling mechanism. This gate-driver chip can drive SiC power FETs of the DC-DC converters in a HEV, and future chip modifications will allow it to drive the SiC power FETs of the traction drive inverter. The converter modules along with the gate-driver chip will be placed very close to the engine where the temperature can reach up to 175ºC. Successful operation of the chip at this temperature with or without minimal heat sink and without liquid cooling will help achieve greater power-to-volume as well as power-to-weight ratios for the power electronics module.

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“…This inflection point is typically known as temperature compensation point (TCP) or zero temperature coefficient (ZTC) [6][7][8][9][10]. Previously, Shoucair [11] and Prijic et al [7] have identified the inflection point for a bulk CMOS in both linear and saturation regions for the temperature varying between 25°C and 200°C. Researchers like Groeseneken et al [9] and Jeon and Burk [1] have experimentally demonstrated the existence of ZTC point for thin and thick film SOI MOSFETs respectively.…”

Section: Introductionmentioning

confidence: 99%