Analytic modeling of potential and threshold voltage for short-channel thin-body fully depleted silicon-on-insulator MOSFETs with a vertical Gaussian doping profile

Abstract

We verify that one-dimensional (1D) Gaussian expression is an appropriate approximation of the vertical doping profile, which is obtained by combining perpendicular ion implantation and rapid thermal annealing (RTA), for short-channel thin-body (20–30 nm) fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. The two-dimensional (2D) potential distribution of the silicon film is derived by adopting the evanescent mode analysis method, in which the potential function is broken into 1D long-channel and 2D short-channel potentials. The threshold voltage model is represented by the minimum front- and back-surface potentials of the silicon film. The application of the threshold voltage model can be extended to a 12 nm channel length. The results obtained using the models match well with the 2D numerical simulation results obtained using the Synopsys Sentaurus Device™. They provide a feasible way of developing new 2D models for nonuniform nanoscale thin-body FD-SOI devices.

Two-dimensional analytical model for fully depleted SOI MOSFETs with vertical trapezoid doping including effects of the interface trapped charges

“…The improvements of the electrical performances such as lower power dissipation, higher speed, as well as reduced SCEs make SOI technology recommended as an important counterpart of the MOSFETs in nanoscale. [6][7][8][9][10] Furtherly, the manufacture of SOI technology is also compatible with that of currently bulk silicon technology. Therefore, numerous researchers have conducted extensive and in-depth research on SOI devices in recent years.…”

“…Since a slight change in the channel doping distribution would results in large changes in electrical performances of the device. [14][15][16][17] Therefore, in order to overcome the shortcomings of abovementioned doping technology, SOI MOSFETs with a vertical Gaussian doping profile 9,18,19) and a vertical trapezoidal doping 20,21) are proposed in the previous works. Gaussian profile can suppress the drain-induced barrier lowering effect, since the peak concentration of the channel in the vertical direction can be controlled to be closer to the buried oxide interface.…”

Combination of volatile and non-volatile functions in a single memory cell and its scalability

“…[10][11][12][13][14][15][16] This is a limitation in scaling down gate length and floating body thickness, because retention properties of floating body effects suffer from short channel effects such as draininduced barrier lowering (DIBL) but PDSOI structure cannot effectively suppress these problems, which results in low-grade retention characteristics of volatile memory function. [17][18][19][20][21][22][23][24][25][26] In this work, a single memory cell having both volatile and non-volatile functions is demonstrated with an independent asymmetric dual-gate and a thin, fully depleted body structure. The volatile memory (VM) can be obtained even in a fully depleted body thanks to the field effect of trapped charges in the nitride layer and the nitride layer allows the non-volatile memory (NVM) in the device at the same time.…”

Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

“…The SOI wafers [5][6][7] with 120 nm crystalline silicon (c-Si) layer were chosen and integrated with a traditional ULSI sub-65 nm generation logic technology to fabricate high aspect-ratio finFETs [8][9][10][11]. The p-channel FinFET devices were fabricated on this kind of SOI wafers.…”