Analysis of interface trap parameters from double‐peak conductance spectra taken on N‐implanted 3C‐SiC MOS capacitors

Krieger, Michael; Beljakowa, Svetlana; Trapaidze, Lia; Frank, Thomas; Weber, Heiko B.; Pensl, Gerhard; Hatta, Natsuo; Abe, Masayuki; Nagasawa, Hiroyuki; Schöner, Adolf

doi:10.1002/pssb.200844062

Cited by 21 publications

(19 citation statements)

References 10 publications

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“…Also, all of the G-V curves have finite FWHM, suggesting that these traps are distributed over an energy range within the bandgap and are not localized at a fixed energy value. Similar results have been reported for nitrogen-implanted 3C-MOS-C. 20 Also, lateral MOSFET were fabricated by use of different oxidation temperatures. The results of mobility measurements for lateral MOSFET are shown in Table I, values of measured field-effect mobility (l) are compared with data previously reported for 3C-SiC MOSFET.…”

Section: Methodssupporting

confidence: 57%

High-Temperature (1200–1400°C) Dry Oxidation of 3C-SiC on Silicon

Sharma

Jennings

et al. 2015

Journal of Elec Materi

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In a novel approach, high temperatures (1200-1400°C) were used to oxidize cubic silicon carbide (3C-SiC) grown on silicon substrate. High-temperature oxidation does not significantly affect 3C-SiC doping concentration, 3C-SiC structural composition, or the final morphology of the SiO 2 layer, which remains unaffected even at 1400°C (the melting point of silicon is 1414°C). Metal-oxide-semiconductor capacitors (MOS-C) and lateral channel metaloxide-semiconductor field-effect-transistors (MOSFET) were fabricated by use of the high-temperature oxidation process to study 3C-SiC/SiO 2 interfaces. Unlike 4H-SiC MOSFET, there is no extra benefit of increasing the oxidation temperature from 1200°C to 1400°C. All the MOSFET resulted in a maximum field-effect mobility of approximately 70 cm 2 /V s.

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Section: Methodssupporting

confidence: 57%

High-Temperature (1200–1400°C) Dry Oxidation of 3C-SiC on Silicon

Sharma

Jennings

et al. 2015

Journal of Elec Materi

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“…By comparing the voltage position of the conductance peaks in the C-V curves, it implies that one of the peaks appears at higher voltage than the flatband voltage, while the other one appears at lower voltage. Then according to the voltage position at which the hump occurs, below the flatband voltage, we can deduce that one of the conductance peaks is due to standard ITs, whereas the other one is due to NIOTs ͑as already reported by Krieger et al 33 ͒. Referring to the bench-marking ͑process 1͒, the anomalous hump and thereby the double conductance peak are even more pronounced for N 2 incorporation during the process steps ͑pro-cesses 2-4͒, showing an enhancement of the NIOT density.…”

Section: G17mentioning

confidence: 81%

Interfacial Properties of Oxides Grown on 3C-SiC by Rapid Thermal Processing

Constant

Camara

Placidi

et al. 2011

J. Electrochem. Soc.

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Interfacial properties of SiO 2 /n-type 3C-SiC structures fabricated by rapid thermal processing have been investigated for various oxidizing and annealing atmospheres. In this work, we show that the growth of SiO 2 films can be, at least, 1 order of magnitude faster than in a conventional furnace. Besides being fast, this technique provides oxide films with quality comparable to those grown in a classical furnace. Analyzing the depth profiles of N and C species in the SiO 2 films and the electrical properties of the oxides, we found that incorporating N 2 during the growth in O 2 or annealing under N 2 is not favorable for the improvement of the SiO 2 /3C-SiC interface. Instead, we demonstrated that combining the beneficial effect of N 2 O oxide growth with the one of Ar anneal, the density of interface traps is reduced and leads to significantly improved oxide quality.Silicon carbide ͑SiC͒ is, by far, the most promising material for high-power and high temperature electronics applications. Compared to other wide bandgap semiconductors, SiC has the unique potential to be thermally oxidized to form a SiO 2 film. This provides a unique opportunity to develop metal oxide semiconductor ͑MOS͒ power devices. 1-3 Compared to the commonly used hexagonal 4H-SiC polytype, the cubic 3C-SiC polytype seems to be more promising with regard to MOS devices because it yields a higher electron mobility and results in a better SiO 2 /3C-SiC interface. With a bandgap of only 2.3 eV compared to 3.2 eV for 4H-SiC, 3C-SiC is regarded as a perfect material for medium power metal-oxide field effect transistors ͑MOSFETs͒.The 3C-SiC polytype has a unique advantage over 4H-SiC: it is the only polytype which can be grown on Si substrates. For this reason, this material was mainly investigated for microelectromechanical systems ͑MEMS͒ application because it allows the easy release of the SiC devices through Si etching. Recently, many works have demonstrated the feasibility of such mechanical devices. 4-6 However, to imagine a possible industrialization of the 3C-SiC MEMS, it is indispensable to dispose of the associated electronics and thus of transistors for the eventual circuitry integration, such as the complementary metal oxide semiconductor extensively used in the Si technology. One of the main issues to realize such circuitry integration is the fabrication of MOSFET devices on 3C-SiC/Si. While many high-performance power MOSFET devices have been demonstrated on 4H-SiC, few devices on 3C-SiC/Si have been demonstrated due to the high defect density in the 3C-SiC epilayers and poorly developed process techniques for 3C-SiC/Si devices. 7 Therefore, several crucial fabrications issues must be solved before truly advantageous 3C-SiC/Si MOSFET devices can be integrated. The gate oxide formation is one key process. When using a standard thermal oxidation the capability to form a grown SiO 2 dielectric with a good quality of the SiO 2 /3C-SiC interface and high oxide reliability is not obvious. 8 As a consequence, for a long time the density of...

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“…2͑b͔͒. Recently, Krieger et al 6 has also reported double-peak conductance spectra for 3C-SiC MOS capacitors fabricated using nitrogen implantation followed by oxidation in pure oxygen. The proposed model 6 attributes two conductance peaks to the presence of two different kinds of interface traps: carbon clusters at the interface ͑energeti-cally shallow states͒ and carbon clusters bound with nitrogen interface donor ͑energetically deep states͒.…”

Section: A 3c-sic Materialsmentioning

confidence: 95%

Advanced oxidation process combining oxide deposition and short postoxidation step for N-type 3C- and 4H-SiC

Esteve

Schöner

Reshanov

et al. 2009

Journal of Applied Physics

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The electrical properties of oxides fabricated on n-type 3C-SiC (001) and 4H-SiC (0001) epilayers using an advanced oxidation process combining plasma enhanced deposition and rapid postoxidation steps have been investigated. Three gas atmospheres have been studied for the postoxidation steps: N2O, dry, and wet oxygen (H2O). In comparison, additional oxides using postannealing in pure N2 have been fabricated. The implementation of wet oxygen resulted in a significant decrease in the interface traps density, in a reduction of oxide fixed charges and in the increased breakdown field in the case of 3C-SiC. In the case of 4H-SiC the postoxidation in N2O is a superior postprocessing step.

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Analysis of interface trap parameters from double‐peak conductance spectra taken on N‐implanted 3C‐SiC MOS capacitors

Cited by 21 publications

References 10 publications

High-Temperature (1200–1400°C) Dry Oxidation of 3C-SiC on Silicon

High-Temperature (1200–1400°C) Dry Oxidation of 3C-SiC on Silicon

Interfacial Properties of Oxides Grown on 3C-SiC by Rapid Thermal Processing

Advanced oxidation process combining oxide deposition and short postoxidation step for N-type 3C- and 4H-SiC

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