Advanced oxidation process combining oxide deposition and short postoxidation step for N-type 3C- and 4H-SiC

Abstract

The electrical properties of oxides fabricated on n-type 3C-SiC (001) and 4H-SiC (0001) epilayers using an advanced oxidation process combining plasma enhanced deposition and rapid postoxidation steps have been investigated. Three gas atmospheres have been studied for the postoxidation steps: N2O, dry, and wet oxygen (H2O). In comparison, additional oxides using postannealing in pure N2 have been fabricated. The implementation of wet oxygen resulted in a significant decrease in the interface traps density, in a reduction of oxide fixed charges and in the increased breakdown field in the case of 3C-SiC. In the case of 4H-SiC the postoxidation in N2O is a superior postprocessing step.

Tailoring the 4H-SiC/SiO2 MOS-interface for SiC-based power switches

“…5, left section) comparable to the thermally grown gate oxides with moderate lowering of the average dielectric breakdown field to 9.2 MV=cm, despite that gate oxides formed by PECVD deposition and subsequent annealing in N 2 O are known to have reduced reliability. 24) The superior reliability of the AGON gate oxide over D-N2O could be related to the high temperature of annealing (1250 °C vs 1150 °C) and corresponding densification of the deposited SiO 2 layer or a healing of oxide defects in pure oxygen at high temperature.…”

Optimization of Poly-silicon Process for 3C-SiC Based MOS Devices

“…1 and Table 1. The solid grey curve represents the D it distribution of a MOS capacitor fabricated by ion beam sputtering of nickel followed by a lift-off lithography process [1]. equal to 3.2 and 3.9 × 10 11 cm -2 , respectively.…”

“…The benefits of the implementation of an advanced oxidation process combining PECVD (Plasma Enhanced Chemical Vapor Deposition) SiO 2 deposition and short post-oxidation steps in wet oxygen has been previously demonstrated [1]. The concentrations of fixed and mobile charges in the oxide and at the SiO 2 /SiC interface were significantly reduced.…”

Impact of Morphological Features on the Dielectric Breakdown at SiO[sub 2]∕3C-SiC Interfaces

“…In addition to the intrinsic properties of the dielectric, the BD event is controlled by defects on the semiconductor surface, the conduction band offset at the semiconductor/SiO 2 interface, and oxidation and post oxidation conditions [3,5]. The nature of the defects, the conduction band offset and the optimal oxidation and post oxidation conditions [6] are different for 3C-SiC compared to the better studied 4H polytype. Hence, a deeper knowledge of the BD generation at the SiO 2 /3C-SiC system is fundamental to understand the device behavior.…”