Optimization of Poly-silicon Process for 3C-SiC Based MOS Devices

Abstract

The electrical properties of wet oxides with poly-silicon gates fabricated on n-type 3C-SiC (001) epilayers have been studied. Five alternatives have been considered for the activation of the poly-silicon layer. The influence of two main parameters has been thought-out: the process type (thermal annealing or rapid thermal annealing) and the gas species composing the annealing atmosphere (argon, dry or wet oxygen). The poly-Si activation process combining RTA and argon as ambient demonstrates minimal thermal budget and superior preservation of the oxide quality. The fabricated MOS structures demonstrate high electrical properties and reliability of the oxide. That results in a small negative flat band voltage shift of -0.9 V and in an interface state density D it of 7.4 × 10 10 eV -1 cm -2 at 0.63 eV below the conduction band. The TZDB measurements revealed an average breakdown electric field of 9.4 MV/cm.