Tailoring the 4H-SiC/SiO₂ MOS-interface for SiC-based power switches

Abstract

In this paper, we compare the performance of lateral MOSFETs fabricated with different gate oxide formation processes on p-type epilayers with doping concentration in the range of 1 × 1016 cm−3 against Al-implanted p-well doped to 1 × 1018 cm−3. An overview of different technological approaches for the enhancement of the channel mobility is provided. The general trends are summarized and concluded and the main guideline for tailoring the gate oxide formation process is discussed.

Cиловой МДП-транзистор на 4H-SiC с эпитаксиальным заглубленным каналом

“…Существуют различные способы снижения сопротивления канала МДП-транзистора [3,4]. Среди них можно выделить (i) уменьшение плотности состояний (ПС) на границе раздела 4H-SiC/SiO 2 , (ii) увеличение концентрации свободных носителей заряда в канале и (iii) уменьшение влияния ПС на транспорт электронов.…”

Evidence for carbon clusters present near thermal gate oxides affecting the electronic band structure in SiC-MOSFET

“…As a reference, we also investigated a MOS structure fabricated by growing a 50 nm gate oxide in a passivating N 2 O atmosphere at 1250 C for 14 h (referred to as pTGO). 17 The top layer contacts of the fabricated MOS capacitors were stripped off using a standard etching solution followed by a subsequent SiO 2 removal cycle in a 2% HF bath. The duration of this HF exposure was systematically controlled in order to analyze the effect of the progressing etch process.…”