Analysis of FPGA/FPIC switch modules

Chang, Yao-Wen; Zhu, Kai; Wu, Guoxing; Wong, Daniel Fu Keung; Wong, Carmen

doi:10.1145/606603.606605

Cited by 5 publications

(2 citation statements)

References 22 publications

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“…Further, by lemma 1, an HSB of size two constructed by algorithm Symmetric_Switch_Block is universal. (If) For an even V, by lemma 5, we can decompose a vector n ¼ (n 1,2 , n 1,3 , y, n 1,6 , n 2,3 , y, n 2,6 , n 3,4 , y, n 3,6 , n 4,5 , n 4,6 , n 5,6 ) into V/2 sub-RRVs n i ¼ (n i, (1,2) , n i, (1,3) , y, n i, (1,6) , n i, (2,3) , y, n i, (2,6) , n i, (3,4) , y, n i, (3,6) , n i, (4,5) , n i, (4,6) , n i, (5,6) ), where i ¼ 1,2, y, V/2, such that each sub-RRV satisfies the following set of inequalities:…”

Section: Proof Of Universalitymentioning

confidence: 99%

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Universal switch blocks for three-dimensional FPGA design

Shyu

Chang

2004

IEE Proc., Circuits Devices Syst.

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The authors consider the switch-block design problem for three-dimensional FPGAs. A three-dimensional switch block M with W terminals on each face is said to be universal if every set of nets satisfying the dimension constraint (i.e. the number of nets on each face of M is at most W) is simultaneously routable through M. A class of universal switch blocks for three-dimensional FPGAs is presented. Each of the switch blocks has 15W switches and switch-block flexibility 5 (i.e. F S =5). It is proved that no switch block with less than 15W switches can be universal. The proposed switch blocks are compared with others of the topology associated with those used in the Xilinx XC4000 FPGAs. Experimental results demonstrate that the proposed universal switch blocks improve routabilty at the chip level. Further, the decomposition property of a universal switch block provides a key insight into its layout implementation with a smaller silicon area.

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Section: Proof Of Universalitymentioning

confidence: 99%

“…Figure 1b illustrates a switch block in which the programmable switches, denoted by dashed lines between terminals, are shown. There are many reports on four-sided switch blocks [2][3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Universal switch blocks for three-dimensional FPGA design

Shyu

Chang

2004

IEE Proc., Circuits Devices Syst.

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Routing architecture optimizations for high-density embedded programmable IP cores

Hallschmid

Wilton

2005

IEEE Trans. VLSI Syst.

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Universal switch blocks for three-dimensional FPGA design

Shyu

Chang

1999

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays

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This research addresses layout issues in FPGA synthesis. We describe a framework for exploiting placement information which reduces compilation time while improving design quality. The framework is general enough to allow designs with generic placement information to adapt to a range of FPGAs with different granularities and routing resources. The key novelty of our approach is the use of placement constraints expressed as polynomial expressions. This method enables constraints to be described and manipulated in a generic way, independent of the size of a circuit. The approach supports various static checks and provides informative user feedbacks on how designs can be improved. A hierarchical resolution engine has been developed to automate the solution of the placement constraint expressions. Prototype implementations of this approach are presented for Xilinx 6200 and Xilinx 4000 devices. Their effectiveness is illustrated by a bit-serial complex multiplier.To counter coarse logic-block granularity and limited routing resources, high-performance design flows for FPGAs often rely on module generators to implement fast sub-circuits. However, the very flexibility of current generator systems makes their automatic use by synthesis and floorplanning steps difficult. We present FLAME, the Flexible API for Module-based Environments, as a solution to these problems. FLAME defines a common model for expressing generator capabilities and module characteristics to module consumers (such as synthesis or floorplanning tools), textual and binary representations for FLAME data, and an API for exchanging FLAME expressions between programs. The API gives consumers access to the module information via a query/reply scheme supporting incremental design refinement. This dynamic approach avoids the explicit enumeration of all design alternatives in static library files, which becomes infeasible for flexible generators. FLAME-compliant module generators and consumers enable the efficient vendor-independent combination of generator-based IP and traditional design tools.In this paper, we consider the switch-block design problem for three-dimensional FPGAs. A three-dimensional switch block M with W terminals on each face is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each face of M is at most W) is simultaneously routable through M. In this paper, we present a class of universal switch blocks for three-dimensional FPGAs. Each of our switch blocks has 15W switches and switch-block flexibility 5 (i.e., Fs = 5). We prove that no switch block with less than 15W switches can be universal. We also compare our switch blocks with others of the topology associated with those used in the Xilinx XC4000 FPGAs. Experimental results demonstrate that our universal switch blocks improve routability at the chip level. Further, the decomposition property of a universal switch block provides a key insight into its layout implementation with a smaller silicon area.

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Analysis of FPGA/FPIC switch modules

Cited by 5 publications

References 22 publications

Universal switch blocks for three-dimensional FPGA design

Universal switch blocks for three-dimensional FPGA design

Routing architecture optimizations for high-density embedded programmable IP cores

Universal switch blocks for three-dimensional FPGA design

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