Universal switch blocks for three-dimensional FPGA design

Abstract

The authors consider the switch-block design problem for three-dimensional FPGAs. A three-dimensional switch block M with W terminals on each face is said to be universal if every set of nets satisfying the dimension constraint (i.e. the number of nets on each face of M is at most W) is simultaneously routable through M. A class of universal switch blocks for three-dimensional FPGAs is presented. Each of the switch blocks has 15W switches and switch-block flexibility 5 (i.e. F S =5). It is proved that no switch block with less than 15W switches can be universal. The proposed switch blocks are compared with others of the topology associated with those used in the Xilinx XC4000 FPGAs. Experimental results demonstrate that the proposed universal switch blocks improve routabilty at the chip level. Further, the decomposition property of a universal switch block provides a key insight into its layout implementation with a smaller silicon area.

Effect of switchbox topologies and net ordering on 3D FPGA routing

“…They also conclude that a higher value of flexibility for the connection block coupled with a lower value of flexibility for the switchbox provide the best results. The authors of [7] presented a proof stating that for three-dimensional switch blocks with W terminals, no switch block with less than 15W switches can be universal. Gayasen et al [3] presented 5 new switchbox topologies including subset-split, universal-twist (for three different via sizes: 3 μm, 5 μm, 10μm) for various bonding technologies.…”

“…In case of 3D (stacked) FPGAs, the inter-layer connections (vertical tracks) are also made through switchboxes and Through Silicon Vias (TSVs) and therefore it is important to evaluate the effect of switchbox architecture on routability for 3D FPGAs. Various studies have looked at 3D switchbox design for FPGAs [2][3] [7]. This study attempts to study the effect of different switchbox architectures and net ordering strategies using the routing delay and the wirelength as metrics.…”

Placement and routing for 3D-FPGAs using reinforcement learning and support vector machines

“…Details of Rothko, a three-dimensional architecture, is discussed in [25]. Universal switch blocks for three-dimensional FPGA design are presented in [8]. Shamik Das et al have explored the performance and wiring requirement for three-dimensional Integration of Field-Programmable Gate Arrays in [6,18].…”