Analysis and Simulation of Schottky Tunneling Using Schottky Barrier FET with 2-D Analytical Modeling

Kumar, Prashanth; Vinod, Adla; Dharavath, Krishna; Bhowmick, Brinda

doi:10.1007/s12633-020-00879-3

Cited by 13 publications

(2 citation statements)

References 20 publications

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“…To overcome the limitations faced by merely shrinking devices, various new architectures have been proposed to continue scaling like SOI MOSFET, double gate MOSFET, tri-gate, step FinFET, and gate all around (GAA) MOSFET. [1][2][3][4][5][6][7][8][9][10] Since 2011, FinFET has emerged as a 3D device chip manufacturer for mass production in electronic industry. 11 Many approaches to enhance the device performance for sub-micron technology have been made, such as channel, gate, doping, and strain engineering techniques.…”

Section: Introductionmentioning

confidence: 99%

“…Scaling decreases the ON current ( I ON ) due to various SCEs and leads to performance degradations. To overcome the limitations faced by merely shrinking devices, various new architectures have been proposed to continue scaling like SOI MOSFET, double gate MOSFET, tri‐gate, step FinFET, and gate all around (GAA) MOSFET 1–10 . Since 2011, FinFET has emerged as a 3D device chip manufacturer for mass production in electronic industry 11 .…”

Section: Introductionmentioning

confidence: 99%

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Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Sreenivasulu

Narendar

2021

Int J RF Mic Comp-Aid Eng

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Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si 3 N 4 , HfO 2 ), and hybrid dual-k (Air + Si 3 N 4 ) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO 2 ) spacer gives a higher switching ratio (I ON /I OFF ) in the order of ~10 7 , subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO 2 ) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si 3 N 4 ) outperforms in terms of gain (A V ) and output resistance (R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m2 , g m3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Sreenivasulu

Narendar

2021

Int J RF Mic Comp-Aid Eng

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Temperature‐Induced Changes in Multifin‐Schottky Barrier FinFETs: An Analog/RF Linearity Investigation

Shalini,

Kumar

2024

Advcd Theory and Sims

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In this script, a Gallium Nitride (GaN)‐based FinFET structure is proposed with a multi‐channel device that is designed and simulated. Here, the 3D‐Sentaures TCAD simulator is used to investigate the analog/radio frequency performance and linearity of the MultiFin‐Schottky Barrier FinFET with different temperatures of 100–400 K. The proposed device underwent a temperature analysis, where critical parameters include drain current, ION/IOFF ratio, Transconductance (gm), higher‐order terms (gm2 and gm3), Gain Bandwidth Product (GBP), Cut‐off Frequency (fT), Transit Time (τ), Transconductance Generation Factor (TGF), Transconductance Frequency Product (TFP), Voltage Input Intercept Point (VIP2, VIP3), Input Intercept Point (IIP3), and Third Order Intermodulation Distortion (IMD3) is thoroughly examined. Thus, the proposed GaN‐based FinFET validates as a strong potential contender for GaN‐based analog/RF applications.

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Dielectric Engineered Schottky Barrier MOSFET for Biosensor Applications: Proposal and Investigation

Singh

Kaim

Medhashree

et al. 2021

Silicon

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Analysis and Simulation of Schottky Tunneling Using Schottky Barrier FET with 2-D Analytical Modeling

Cited by 13 publications

References 20 publications

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Temperature‐Induced Changes in Multifin‐Schottky Barrier FinFETs: An Analog/RF Linearity Investigation

Dielectric Engineered Schottky Barrier MOSFET for Biosensor Applications: Proposal and Investigation

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