Analysis and optimization of NBTI induced clock skew in gated clock trees

Chakraborty, Samarjit; Ganesan,; Rajaram,; Jian, Pan

doi:10.1109/date.2009.5090675

Cited by 19 publications

(11 citation statements)

References 9 publications

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“…Also, when the skew degradations is large, the use of the technique may not be practical [15]. A technique for equalizing the signal probability (SP) of all clock tree trunks for balancing the NBTI stress is presented in [26]. In addition, to estimate the NBTI effect, a compact formula for computing equivalent temperatures under a Gaussian temporal temperature variation is proposed.…”

Section: Previous Workmentioning

confidence: 99%

CSAM: A clock skew-aware aging mitigation technique

Eghbalkhah

Kamal

Afzali-Kusha

et al. 2015

Microelectronics Reliability

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Section: Previous Workmentioning

confidence: 99%

CSAM: A clock skew-aware aging mitigation technique

Eghbalkhah

Kamal

Afzali-Kusha

et al. 2015

Microelectronics Reliability

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“…This scenario accelerates a process of transistor performance degradation (called ageing). Extensive usage of clock gates in the design for power reduction [8,9] causes portions of the clock tree to be inactive at different points in time, resulting in differential ageing scenarios on the clock tree. If some of the clocks are kept gated at all times during the burnin process, there can result an asymmetric stress of N & P transistors causing the additional N/P strength mismatches that can give rise to duty cycle distortion.…”

Section: Clock Distortion Due To Local Mismatchesmentioning

confidence: 99%

A Silicon Testing Strategy for Pulse-Width Failures

Vooka

Agarwal

Shrivastava

et al. 2012

2012 25th International Conference on VLSI Design

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With the increasing clock frequencies to multiple Gigahertz and increasing need to achieve it at lower voltages for keeping operating power lower, frequency of operation is not only limited by the datapath delay scaling but also by the behavior of clock signals. Failures induced by violation of minimum clock pulse width required, at higher frequencies is more commonly seen due to increased operating frequencies and usage of voltage scaling techniques for achieving higher frequencies [1]. Silicon failures caused by minimum pulse width violation due to clock shrinkage can be due to variety of reasons right from duty cycle distortion at clock generator (PLL) to clock pulse distortion due to slew degradation along the clock path. In this paper authors discuss different techniques that enable us to minimize pulse width failures as the mechanism that limit the frequency of operation of the device. In this paper we propose a simple and novel technique to detect and diagnose pulse width failures. Silicon results from 40nm multi-million gate industrial SoC is presented to indicate the effects of pulse width degradation on performance of the device and to evaluate the effectiveness of the proposed pattern generation technique.

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“…13. The ICG cell proposed in [5]. gating probability, the method may aggravate rather than reduce N/PBTI-induced skew.…”

Section: Related Workmentioning

confidence: 99%

“…al. [5] proposed an ICG cell design (see Fig. 13) that can alternate the clock state based on an external signal AUX.…”

Section: Related Workmentioning

confidence: 99%

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BTI-Gater: An Aging-Resilient Clock Gating Methodology

Lai

Chandra

Aitken

et al. 2014

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-Negative-and Positive-Bias Temperature Instability (N/PBTI) have become one of the most important reliability issues in modern semiconductor technology. N/PBTI-induced degradation depends heavily on workload, which causes imbalanced degradation and additional clock skew for clock distribution networks with clock gating features. In this work, we first analyze the effects of N/PBTI on clock paths with different clock gating use cases. Then cross-layer solutions are proposed to reduce N/PBTI-induced clock skew. Two Integrated Clock Gating (ICG) cell circuits are proposed to alternate clock idle state between logic high and logic low for each clock gating operation. A skew mitigation methodology is also proposed to select the appropriate ICG cells based on the architecture and microarchitecture context. An example of sleep scheduling is also described as a simple software-level technique that can be used in conjunction with BTI-Gater to avoid certain pathological aging scenarios. Our experiments show that BTI-Gater can balance the gated clock branches to close to 50% signal duty ratio, while guaranteeing a glitch-free clock signal with easy-to-verify timing constraints. Results on commercial processors show that BTIGater can effectively reduce N/PBTI-induced clock skew of up to 17ps, which can be converted to up to 19.7% leakage power saving compared to pure design guardbanding.

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Analysis and optimization of NBTI induced clock skew in gated clock trees

Cited by 19 publications

References 9 publications

CSAM: A clock skew-aware aging mitigation technique

CSAM: A clock skew-aware aging mitigation technique

A Silicon Testing Strategy for Pulse-Width Failures

BTI-Gater: An Aging-Resilient Clock Gating Methodology

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