An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

Pilo, H.; Barwin, J.; Braceras, G.; Browning, Clyde; Burns, Steven; Gabric, J.; Lamphier, S.; Miller, M.; Roberts, A.; Towler, F.

doi:10.1109/vlsic.2006.1705289

Cited by 74 publications

(31 citation statements)

References 4 publications

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“…This WA scheme is implemented using a second external lower supply which is connected via a multiplexer to the write-selected columns [15]. On-chip regulators can also be used to generate the lower supply voltage during write [8].…”

Section: Sram Write-ability Metricmentioning

confidence: 99%

On the efficacy of write-assist techniques in low voltage nanoscale SRAMs

Chandra¹,

Pietrzyk²,

Aitken³

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Read and write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. In this paper, we review the efficacy of four leading write-assist (WA) techniques and their behavior at lower supply voltages in commercial SRAMs from 65nm, 45nm and 32nm low power technology nodes. In particular, the word-line boosting and negative bit-line WA techniques seem most promising at lower voltages. These two techniques help reduce the value of W Lcrit by a factor of ∼2.5X at 0.7V and also decrease the 3σ spread by ∼3.3X, thus significantly reducing the impact of process variations. These write-assist techniques also impact the dynamic read noise margin (DRNM) of half-selected cells during the write operation. The negative bit-line WA technique has virtually no impact on the DRNM but all other WA techniques degrade the DRNM by 10-15%. In conjunction with the benefit (decrease in W Lcrit) and the negative impact (decrease in DRNM), overhead of implementation in terms of area and performance must be analyzed to choose the best write-assist technique for lowering the SRAM Vmin.

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Section: Sram Write-ability Metricmentioning

confidence: 99%

On the efficacy of write-assist techniques in low voltage nanoscale SRAMs

Chandra¹,

Pietrzyk²,

Aitken³

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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“…Some of these techniques rely on boosted word line voltage [10]- [12], reducing the supply voltage VDD [8]- [9], [13]- [14], sizing cell transistors [15]- [17], reduced bit line voltage [18]- [19], and raising the source voltage V SS [20]- [22]. However, each of these techniques may cause a reduction in the drive current of the transistors and in the operating speed of the cell, or has increased memory cell area and a degradation in the manufacturing accuracy, or requires generation of a voltage above the operating voltage, or requires a more complicated circuit design and more complicated device process.…”

Section: Existing 6t and 5t Sram Cell Topologiesmentioning

confidence: 99%

Single-Port 5T SRAM Cell with Improved Write-Ability and Reduced Standby Leakage Current

Yu¹,

Shiau²

2017

IJIEE

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Abstract-In this paper, a novel single-port five-transistor (5T) Static Random Access Memory (SRAM) cell and associated read/write assist is proposed. Amongst them, a voltage level conversion circuit is to provide a voltage of the respective connected word line to be lower than or equal to the power supply voltage VDD, as such the read/write-ability of the cell can be improved. Furthermore, a voltage control circuit is coupled to the sources corresponding to the driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. In addition, a pre-charging circuit is design to pull up the bit line BL of a selected column to the voltage VDD before the read or write operation. Finally, with the standby start-up circuit design, the memory cell can rapidly switch to the standby mode, and thereby reduce leakage current in standby. In particular, the paper introduce a two-phase reading mechanism to improve the reading speed, and thus to avoid unnecessary power consumption. Furthermore, by using the voltage level conversion circuit to pull the voltage of the signal WLC in a selected row cells lower than the power supply voltage VDD by a threshold voltage during a read operation, thereby to reduce the half-selected cells disturbance.Index Terms-Read/write assist circuitry, standby start-up circuit, static random access memory, voltage level conversion circuit, voltage control circuit.

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“…Also, there are serious concerns about the continued scalability of SRAM-based memories [3]. Several groups have proposed solutions to patch stability issues due to process variations in memory designs that use 6T SRAM cells [14,25].…”

Section: Related Workmentioning

confidence: 99%