Process Variation Tolerant 3T1D-Based Cache Architectures

Mutlu, Onur; Moscibroda, Thomas

doi:10.1109/micro.2007.40

Cited by 277 publications

(54 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…For memory dominated structures, the SRAM array lookups have significantly more regularity and allow for dynamic partitioning and resizing which may allow them to improve performance in an energy-efficient manner by sacrificing capacity [30]. There has been a significant amount of work in adapting SRAM structures for use in both lowvoltage modes and severe parameter variation [25,30,31]. In contrast, logic dominated structures in the processor backend, most notably execution units, would be difficult to accelerate without significant impact to the power budget.…”

Section: Background and Motivationmentioning

confidence: 99%

Identifying and predicting timing-critical instructions to boost timing speculation

Xin¹,

Joseph²

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins and eliminating power/performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. To a large extent existing work has relied on statistical error models and has not evaluated potential disparity of error rates at the level of static instructions. In this paper, we analyze gatelevel hardware models for an execution pipeline and demonstrate pronounced locality in instruction-level error rates due to value locality and data dependences. We propose timing error prediction to dynamically anticipate timing errors at the instruction-level and error padding techniques to avoid the full recovery cost of timing errors. We show that with simple prediction strategies our mechanism can reduce 80% of the performance penalty incurred by error recovery on average. This allows us to alleviate some limitations of timing speculation and improves energy-efficiency by 21% when compared to baseline timing speculation techniques using the same dynamic adaptive tuning mechanism.

show abstract

Section: Background and Motivationmentioning

confidence: 99%

Identifying and predicting timing-critical instructions to boost timing speculation

Xin¹,

Joseph²

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

show abstract

“…In the e-DRAM cell, if the driving capability of the access transistor is reduced due to variations, the access speed of the cell will reduce. However, this effect can otherwise be viewed as a shorter retention time with unchanged access speed, as discussed in detail in [11]. The speed of an eDRAM cell gradually slows down after refresh.…”

Section: Process Variation Impact On Memorymentioning

confidence: 99%

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

JingNaifeng

ShenYao

LuYao

et al. 2013

SIGARCH Comput. Archit. News

Self Cite

View full text Add to dashboard Cite

The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for traditional S-RAM designs in the future technologies. In this paper, we propose to use embedded-DRAM (eDRAM) as an alternative in future GPGPUs. Compared with SRAM, eDRAM provides higher density and lower leakage power. However, the limited data retention time in eDRAM poses new challenges. Periodic refresh operations are needed to maintain data integrity. This is exacerbated with the scaling of eDRAM density, process variations and temperature. Unlike conventional CPUs which make use of multi-ported RF, most of the RFs in modern GPGPU are heavily banked but not multi-ported to reduce the hardware cost. This provides a unique opportunity to hide the refresh overhead. We propose two different eDRAM implementations based on 3T1D and 1T1C memory cells. To mitigate the impact of periodic refresh, we propose two novel refresh solutions using bank bubble and bank walk-through. Plus, for the 1T1C RF, we design an interleaved bank organization together with an intelligent warp scheduling strategy to reduce the impact of the destructive reads. The analysis shows that our schemes present better energy efficiency, scalability and variation tolerance than traditional SRAM-based designs.

show abstract

“…Liang et. al [28] proposed the 3T1D (three transistors and a diode) DRAM cell. The speed of these cells is comparable to the speed of 6T SRAM cells.…”

Section: Leakage Reduction In Sram Cachesmentioning

confidence: 99%

“…The scrub operation can be implemented with a single binary counter [23,28] for the entire cache, initialized to the retention time divided by the total number of eDRAM blocks in the cache, and guarantees that all eDRAM blocks are checked (i.e., written back if dirty and invalidated) before the retention time expires. The impact of bank contention on performance is minimal because, i) most accesses hit in SRAM banks,…”

Section: High-performance Modementioning

confidence: 99%

Cache architectures based on heterogeneous technologies to deal with manufacturing errors

Garcés¹,

Jesús²

View full text Add to dashboard Cite

AgraïmentsDurant la realització d'aquesta tesi he passat per períodes difícils en els quals he trobat el recolzament incondicional dels meus directors, Julio i Salva. A ells els vull agrair la seua paciència i comprensió durant aquests anys, però sobretot elsànims que m'han donat per a que continuara endavant amb aquest projecte.També estic molt agraït a Alex, amb el que he col·laborat en diferents articles. A més a més m'ha oferit sempre la seua ajuda donant-me una resposta ràpida a qualsevol dubte que li he plantejat.Moltes gràcies als tres!

show abstract

Process Variation Tolerant 3T1D-Based Cache Architectures

Abstract: Abstract

Cited by 277 publications

References 22 publications

Identifying and predicting timing-critical instructions to boost timing speculation

Identifying and predicting timing-critical instructions to boost timing speculation

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

Cache architectures based on heterogeneous technologies to deal with manufacturing errors

Contact Info

Product

Resources

About