An Oxide-Buffered BE-MANOS Charge-Trapping Device and the Role of Al2O3

Lai, Sheng-Chih; Lue, Hang-Ting; Liao, Chien-Wei; Huang, Ya-Chi; Yang, Ming-Jui; Lue, Yi-Hsien; Wu, Tai–Bor; Hsieh, Jung-Yu; Wang, Szu-Yu; Hong, Shih-Ping; Hsu, Fang-Hao; Shen, Chili-Yen; Luo, Guang-Li; Chien, Chao–Hsin; Hsieh, Kuang-Yeu; Liu, R.; Lu, Chih Yuan

doi:10.1109/nvsmw.2008.35

Cited by 9 publications

(4 citation statements)

References 2 publications

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“…MANOS/TANOS [7] solves this problem by using a high-K top dielectric (such as Al 2 O 3 ). It has been clarified [8] that the primary function of high-K top blocking oxide is to suppress the E field and gate electron injection. Thus the erase saturation of MANOS/TANOS is much lower than SONOS/MONOS, allowing a suitable memory window.…”

Section: Planar 2d Charge-trapping (Ct) Devicesmentioning

confidence: 99%

“…Again, the thick non-optimized high-K Al 2 O 3 also causes additional reliability problems thus we find that the best way to improve the reliability is to insert a sufficiently thick buffer oxide in between Al 2 O 3 and SiN, and also minimize the high-K thickness to reduce the bulk trapped charges. The optimized BE-MAONOS [8] shows a large memory window with good reliability. The theoretical model of the general barrier engineered (BE) CT devices has already been developed [12].…”

Section: Planar 2d Charge-trapping (Ct) Devicesmentioning

confidence: 99%

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State-of-the-art flash memory devices and post-flash emerging memories

Lue

Chen

2011

Sci. China Inf. Sci.

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Although conventional Floating gate (FG) flash memory has recently gone into the 2X nm node, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (multi-level cell, or more than one bit storage per cell) storage. However, due to the simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels), CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1Xnm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues. Devices that do not rely on charge storage are naturally not limited by the number of electrons, thus promise further scaling below 10 nm. Several of the most promising post-flash era devices, their operation principle and critical issues are reviewed. (One of them, phase change memory, will be covered in a separate article thus not included here.) Their potential applications and challenges for 3D stacking are critically examined. State-of-the-art floating gate flash memoryFlash memories have become ubiquitous in consumer electronics, mobile devices and PC and enterprise applications [1]. The basic operation principle of flash memory device is to store electrons in a floating gate (FG) or a charge-trapping layer (such as SONOS) and accordingly the Vth of the MOSFET devices is changed and identified as the stored logic state. The older EEPROM (electrically erasable and programmable read only memory) uses two transistors to provide RAM-like random access and bit alterable features. Flash memory gives up the bit alterable feature and adopts a block erase (flash) to achieve a 1-transistor (1T) cell that allows much higher density. Over the years, the array architecture has converged into NOR and NAND types (Figure 1) for different applications.NOR Flash device uses channel hot electron (CHE) injection for programming and has retained fast random access capability suitable for code storage applications. The random access feature requires a

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Section: Planar 2d Charge-trapping (Ct) Devicesmentioning

confidence: 99%

Section: Planar 2d Charge-trapping (Ct) Devicesmentioning

confidence: 99%

State-of-the-art flash memory devices and post-flash emerging memories

Lue

Chen

2011

Sci. China Inf. Sci.

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“…These developments require a considerably tighter distribution of the cell threshold voltage (VTH) and high-immune and retention characteristics. A bandgap-engineered tunneling oxide (BE-TOX) layer and block layer have been introduced to enhance the program/erase (P/E) speed and retention reliability, replacing the conventional SiO2 layer [3][4].…”

Section: Introductionmentioning

confidence: 99%

Impact of P/E Stress on Trap Profiles in Bandgap-Engineered Tunneling Oxide of 3D NAND Flash Memory

Yoon

Park

et al. 2022

IEEE Access

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The quantitative characteristics of traps created in the bandgap-engineered tunneling oxide (BE-TOX) layer and block layer after program/erase (P/E) stress-cycling in a 3D NAND flash memory were investigated. The trap spectroscopy by charge injection and sensing technique was used to obtain the distribution of traps in these layers. In the BE-TOX layer, significant traps were generated at 1.3 eV in the nitrogen-doped layer (N1) and increased by 48% in the fresh cell after P/E stress-cycling. The H bonds in the N1 are more likely to break during the stress-cycling and create neutral ≡ SiO • traps. In the block layer, however, trap generation was negligible after stress-cycling.INDEX TERMS 3D NAND flash memory, bandgap-engineered tunneling, program/erase cycling, trap profile, TSCIS

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“…as shown in Figures 7,8,9. In order to effectively utilize the P/E benefits from BE-TO and/or BE-SiN x , improving Cret has to be addressed. Both BE-BL (6) and oxygen-bearing high EWF electrodes (7,8) can be used to improve retention. Thus, the best performing MANOS device is expected from carefully combining the optimization efforts for its individual components to maximize P/E & endurance while maintaining low loss Cret.…”

Section: Introductionmentioning

confidence: 99%

Engineering the complete MANOS-type NVM stack for best in class retention performance

Gilmer¹,

Goel²,

Park³

et al. 2009

2009 IEEE International Electron Devices Meeting (IEDM)

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We demonstrate best in class performance for MANOStype charge-trap flash non-volatile memory devices through improved program/erase (P/E), endurance and retention. Band-engineered (BE) tunnel-oxides (TO) and BE-SiN x charge-trap layers are employed to optimize program, erase, and endurance with trade-off in retention. However, for the 1st time we combine BE-TO, BE-SiN x , BE-blocking layer (BE-BL) and an oxygen-bearing high effective-work-function (EWF) electrode to dramatically improve retention while maintaining the combined benefits from the engineering of each individual stack component. Resulting device improvements include larger ΔVth P/E windows of >300%, enduring P/E cycles to at least 100K cycles while maintaining a window >4V, and retention approaching zero% charge loss over 24 hours at 150ºC. The large, enduring windows with improved retention are favorable for multi-level cell application beyond the 30nm node.

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An Oxide-Buffered BE-MANOS Charge-Trapping Device and the Role of Al2O3

Cited by 9 publications

References 2 publications

State-of-the-art flash memory devices and post-flash emerging memories

State-of-the-art flash memory devices and post-flash emerging memories

Impact of P/E Stress on Trap Profiles in Bandgap-Engineered Tunneling Oxide of 3D NAND Flash Memory

Engineering the complete MANOS-type NVM stack for best in class retention performance

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