Engineering the complete MANOS-type NVM stack for best in class retention performance

Abstract

We demonstrate best in class performance for MANOStype charge-trap flash non-volatile memory devices through improved program/erase (P/E), endurance and retention. Band-engineered (BE) tunnel-oxides (TO) and BE-SiN x charge-trap layers are employed to optimize program, erase, and endurance with trade-off in retention. However, for the 1st time we combine BE-TO, BE-SiN x , BE-blocking layer (BE-BL) and an oxygen-bearing high effective-work-function (EWF) electrode to dramatically improve retention while maintaining the combined benefits from the engineering of each individual stack component. Resulting device improvements include larger ΔVth P/E windows of >300%, enduring P/E cycles to at least 100K cycles while maintaining a window >4V, and retention approaching zero% charge loss over 24 hours at 150ºC. The large, enduring windows with improved retention are favorable for multi-level cell application beyond the 30nm node.

Explanation of the Charge Trapping Properties of Silicon Nitride Storage Layers for NVMs—Part II: Atomistic and Electrical Modeling

“…The dependence of the memory operation on the SiN composition has already been documented by many authors [1], [2], [4]- [6], but it should be said that a convincing explanation of the tradeoff between erase and retention performance has not been conclusively addressed. In particular, to explain the faster erase speed and the smaller retention time of Si-rich SiN cells, some authors invoke electron traps that are shallower in energy with respect to those present in cells with std SiN trapping layers [2], [7].…”

Atomistic Design of Guiding Principles for High Quality Metal–Oxide–Nitride–Oxide–Semiconductor Memories: First Principles Study of H and O Incorporation Effects for N Vacancies in SiN Charge Trap Layers

“…consistent with a recent report. 4) The instability of the incorporation of two H atoms is caused mainly by geometrical restriction, where the vacancy site cannot provide enough space for incorporating more than two H atoms. Actually, in the optimized geometry of a two Hincorporated N vacancy model (Fig.…”

“…3) However, charge traps on an atomic scale intrinsically induce a memory degradation. 4,5) Indeed, we have recently pointed out that there are two types of structural change caused by program/erase (P/E) operations in charge trap memories. 6) One is a reversible structural change which takes a system back to the original position after the P/E operations [Fig.…”

Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

“…[3][4][5][6] Among these structures, the charge trapping memory (CTM) shows the most excellent potential as one of the most promising candidates for future memory solutions. [7][8][9] Furthermore, in recent years, high-density CTM in three-dimensional (3D) architectures for the NAND applications has drawn a great deal of attention. [10][11][12] Under this circumstance, understanding the physical mechanisms in CTM has growing importance in terms of designing and optimizing CTM devices.…”