An overview of D-I algebra

Josephs, Mark B.; Udding, Jan Tijmen

doi:10.1109/hicss.1993.270632

Cited by 31 publications

(13 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To be able to build complex systems one must use more complex components, which are "externally" delay insensitive, while "internally" are designed by carefully verifying their timing and avoiding or tolerating metastability [13,17,26]. By slightly relaxing the unbounded delay model and allowing "isochronic forks" 2 , practical quasi-delay-insensitive circuits can be built using simple logic gates [3].…”

Section: Latency Insensitive Vs Asynchronous Designmentioning

confidence: 99%

A Methodology for Correct-by-Construction Latency Insensitive Design

et al. 2003

View full text Add to dashboard Cite

show abstract

Section: Latency Insensitive Vs Asynchronous Designmentioning

confidence: 99%

A Methodology for Correct-by-Construction Latency Insensitive Design

et al. 2003

View full text Add to dashboard Cite

show abstract

“…The method requires us to model explicitly the wires that form a Foam Rubber Wrapper, as in [3]. In contrast, [8] introduced a special-purpose calculus, DI-algebra, in which every process is implicitly DI.…”

Section: Discussionmentioning

confidence: 97%

Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench

Kapoor

Josephs

2004

Information Processing Letters

View full text Add to dashboard Cite

“…However, it has been proven that almost no useful delay-insensitive circuits can be built if one is restricted to a class of simple logic gates [22], [23]. To be able to build complex systems, one must use more complex components, which are "externally" delay insensitive, while "internally" are designed by carefully verifying their timing and avoiding or tolerating metastability [20], [24], [25]. By slightly relaxing the unbounded delay model and allowing "isochronic forks," 1 practical quasi-delay-insensitive circuits can be built using simple logic gates [26].…”

Section: Background and Related Workmentioning

confidence: 99%

Theory of latency-insensitive design

Carloni

McMillan

Sangiovanni-Vincentelli

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

342

245

View full text Add to dashboard Cite

Abstract-The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components. Latency-insensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol. The protocol works on the assumption that the modules are stallable, a weak condition to ask them to obey. The goal of the protocol is to guarantee that latency-insensitive designs composed of functionally correct modules behave correctly independently of the channel latencies. This allows us to increase the robustness of a design implementation because any delay variations of a channel can be "recovered" by changing the channel latency while the overall system functionality remains unaffected. As a consequence, an important application of the proposed theory is represented by the latency-insensitive methodology to design large digital integrated circuits by using deep submicrometer technologies.Index Terms-Deep submicrometer design, formal methods, latency-insensitive protocols, system design.

show abstract

An overview of D-I algebra

Cited by 31 publications

References 9 publications

A Methodology for Correct-by-Construction Latency Insensitive Design

A Methodology for Correct-by-Construction Latency Insensitive Design

Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench

Theory of latency-insensitive design

Contact Info

Product

Resources

About