Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench

Kapoor, Hemangee K.; Josephs, Mark B.

doi:10.1016/j.ipl.2003.12.007

Cited by 10 publications

(6 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In theory, various authors [8,10,12] have abstracted from the interaction of different layers by using data structures based on a particular level of abstraction. For example, to model delay insensitive (DI) circuits, which are at a lower level of abstraction (physical layer), wires are used as a buffering mechanism [11]. On the other hand to model data flow networks, which are at a higher level of abstraction (in comparison to DI circuits), queues are used as a buffering mechanism [10].…”

Section: Architecturementioning

confidence: 99%

See 1 more Smart Citation

A theory of desynchronisable closed loop system

Beohar¹,

Cuijpers²

2010

Electron. Proc. Theor. Comput. Sci.

View full text Add to dashboard Cite

The task of implementing a supervisory controller is non-trivial, even though different theories exist that allow automatic synthesis of these controllers in the form of automata. One of the reasons for this discord is due to the asynchronous interaction between a plant and its controller in implementations, whereas the existing supervisory control theories assume synchronous interaction. As a consequence the implementation suffer from the so-called inexact synchronisation problem. In this paper we address the issue of inexact synchronisation in a process algebraic setting, by solving a more general problem of refinement. We construct an asynchronous closed loop system by introducing a communication medium in a given synchronous closed loop system. Our goal is to find sufficient conditions under which a synchronous closed loop system is branching bisimilar to its corresponding asynchronous closed loop system.

show abstract

Section: Architecturementioning

confidence: 99%

“…In the past, the idea of solving a refinement problem was studied [8,10,11], but different setups (in comparison with the current paper) were used in these studies. These studies were motivated by the so-called "Foam-rubber wrapper" principle [15], borrowed from the field of delay insensitive circuits.…”

Section: Introductionmentioning

confidence: 99%

A theory of desynchronisable closed loop system

Beohar¹,

Cuijpers²

2010

Electron. Proc. Theor. Comput. Sci.

View full text Add to dashboard Cite

show abstract

“…As regards the verification of asynchronous circuits and architectures, we distinguish two lines of related work: -A first line of work focusses on the verification of asynchronous designs without paying attention to synthesis. In these approaches, the asynchronous designs are specified in the input language of the verification tool to be used, such as Promela for Spin [40,41], Ccs for Cwb [42,43], Lotos for Cadp [44][45][46], or Csp for Fdr2 [47,48]. These approaches target gate level descriptions of asynchronous circuits [40][41][42][44][45][46][47][48] or explicitly model of wires of unbounded delay [43].…”

Section: Related Workmentioning

confidence: 99%

On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP

Garavel

Salaün

Serwe

2009

Science of Computer Programming

View full text Add to dashboard Cite

Hardware process calculi, such as Chp (Communicating Hardware Processes), Balsa, or Haste (formerly Tangram), are a natural approach for the description of asynchronous hardware architectures. These calculi are extensions of standard process calculi with particular synchronisation features implemented using handshake protocols. In this article, we first give a structural operational semantics for value-passing Chp. Compared to the existing semantics of Chp defined by translation into Petri nets, our semantics is general enough to handle value-passing Chp with communication channels open to the environment, and is also independent of any particular (2-or 4-phase) handshake protocol used for circuit implementation. We then describe the translation of Chp into the process calculus Lotos (ISO standard 8807), in order to allow asynchronous hardware architectures expressed in Chp to be verified using the Cadp verification toolbox for Lotos. A translator from Chp to Lotos has been implemented and successfully used for the compositional verification of two industrial case studies, namely an asynchronous implementation of the Des (Data Encryption Standard) and an asynchronous interconnect of a NoC (Network on Chip).

show abstract

“…As regards the application of model checking tools to asynchronous hardware designs in general, most approaches, e.g., [25,7,13,16,27,31,32], are based on a manual modelling of the design directly in the input language of the used verification tool, whereas we base the verification on design descriptions written by hardware designers -the same descriptions that are also used for synthesizing the circuits. As an example, [31] introduces a model for the low-level description of asynchronous circuits on the hardware gate level, and presents the verification of safety and progress properties using FDR2 (via a manual translation to CSP).…”

Section: Related Workmentioning

confidence: 99%