An overview of 3D integrated circuits

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

“…This can also be exploited to increase the pixels for the same area in order to increase the full well capacity. Stacked imagers, however, also have several challenges [3], [8]:…”

“…Since the focus of FoM 3D is on the ADC performance, FoM 3D only includes the power consumption of the ADC. In the FoM CIS definition of ( 13), the speed of the imager is measured by the pixel rate (= N H • N V • FR), which depends on A pixel /(A ADC • T * ADC ) according to (8). As a consequence, A pixel /(A ADC • T * ADC ) is included as speed factor in the definition of FoM 3D .…”

Dielectric-on-Dielectric Achieved on SiO2in Preference to W by Water-free Chemical Vapor Depositions with Aniline Passivation

“…The current 3-D integrated circuit (IC) requires multilayer circuits bonded together by interconnects. The advantage of 3-D integration comes from the decrease in the interconnect length, which leads to higher performance and lower power consumption. − Despite the advantages of 3-D IC, it is also facing several challenges such as heat removal, power delivery, and interconnect misalignment. , This interconnect misalignment is one of the major limitations of IC performance and scaling process due to limited via to metal line distance which leads to shorting or capacitive coupling between the via and the metal …”

Remote Gating of Schottky Barrier for Transistors and Their Vertical Integration

“…The gapless electronic structure of graphene, which exhibits linear energy dispersion near the Dirac voltage, permits the development of an unconventional device architecture. − In particular, graphene can be exploited as the electrode that yields a tunable semiconductor–electrode injection barrier as the Fermi energy level of graphene can be tuned widely by the application of an external electric field. − This mechanism sets the basis for graphene-based vertical Schottky barrier transistors (v-SBTs); the current level of these devices can be changed by controlling the SB height via tuning the gate bias. − Such a vertical transistor structure is expected to trigger a paradigm shift in electronic device architecture and associated circuit design. A vertical channel, unlike the lateral channel used in conventional transistors, can, in principle, mitigate the challenges to achieving a nanoscale channel length as the channel length can be determined simply from the thickness of the semiconductor layer. ,,− Furthermore, the vertical configuration of the unit transistor may facilitate the integration of multiple devices in an entirely different vertical scheme. − Vertical stacking of unit devices does not consume additional chip estate beyond what is needed for a single device placed at the bottom. , Moreover, the vertically integrated devices based on layer-by-layer stacking of functional materials do not require saving a well spacing between the n- and p-channels, which is necessary in the conventional lateral-type CMOS technology to prevent crosstalk between the complementary channels and to avoid latch up. In fact, a common design rule for the well spacing is to separate the n- and p-MOSFET channels by 6 times the minimum width of the line, whereas the vertically stacked channels from additive processes do not require this consideration.…”