An optimization of AND-OR-EXOR three-level networks

Debnath, Debatosh; Sasao, Tsutomu

doi:10.1109/aspdac.1997.600332

Cited by 19 publications

(19 citation statements)

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“…Design methods for adders by using AND-OR-EXOR PLAs with more than one-bit input decoders were developed at IBM [32]. Exact minimization algorithms for EX-SOPs and upper bounds on the number of products in EX-SOPs are also reported [4]- [6], [9]. AND-OR-EXOR networks where output EXOR gates have unlimited fan-in is considered [27].…”

Section: Introductionmentioning

confidence: 99%

Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders

Debnath

Sasao

2005

IEICE Transactions on Information and Systems

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Debatosh DEBNATH †a) , Nonmember and Tsutomu SASAO † †b) , Member SUMMARY This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-ofproducts expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EXSOPs where some outputs of the function are minimized in the complemented form and presented techniques to minimize EX-SOPs for adders by using an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. The proposed algorithm produces solutions with a half products of AOXMINlike algorithm in 250 times shorter time for large adders with two-valued inputs. We also proved that an n-bit adder with two-valued inputs requires at most 3 · 2 n−2 + 7n − 5 products in an EX-SOP while it is known that a sum-of-products expression (SOP) requires 6 · 2 n − 4n − 5 products. key words: three-level network, logic minimization, adder, programmable logic IntroductionProgrammable logic arrays (PLAs) with two-input EXOR gates at the outputs, also known as AND-OR-EXOR PLAs ( Fig. 1) [28], are a powerful architecture to realize many logic functions. The AND-OR-EXOR PLA realizes an EXOR of two sum-of-products expressions (EX-SOP). Minimization of the number of products in EXSOPs is an important step in the optimization of AND-OR-EXOR PLAs, because the number of products is directly related to the cost of PLAs. EX-SOPs are promising because, for many practical logic functions, they often require many fewer products than sum-of-products expressions (SOPs) [7], [10], [11], [15], [16], [28].AND-OR-EXOR three-level networks are suitable for implementing adders, which serve as building blocks for synthesizing many other arithmetic circuits [21]. For example, Texas Instruments' SN181 arithmetic circuit and SN283 four-bit adder have two-input EXOR gates in the outputs [31]; Monolithic Memories' ZHAL20X8A eight-bit counter realizes EX-SOPs [19]. An AND-OR-EXOR is one of the simplest three-level architecture, since it contains only a single two-input EXOR gate. However, its logic capabil- ity is quite high. Because of this, various programmable logic devices (PLDs) with two-input EXOR gates in the outputs were developed. Important contributions of the paper are as follows:• We present a method to reduce the number of products in EX-SOPs by considering output phase optimization [26], where some components of the function are implemented in the complemented form.• We develop a heuristic method to minimize EX-SOPs for adders with two-and four-valued inputs by using an extension of the AOXMIN algorithm [10].• We proved that an n-bit adder with two-valued inputs requires at most 3·2 n−2 +7n−5 products in an EX-SOP.A crucial step in AOXMIN is to partition the products of an SOP of the given function into two sets, which is done by a random method. We propose a partitioning method for adders. Our experimental result demonstrates that, for an n-bit adder w...

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Section: Introductionmentioning

confidence: 99%

Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders

Debnath

Sasao

2005

IEICE Transactions on Information and Systems

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“…A cut-and-try method was reported in [16] and a table look-up based heuristic algorithm to simplify EX-SOPs was shown in [4]. Several heuristic algorithms to simplify EX-SOPs were presented in [22], which also showed the benchmark results for EX-SOPs for the first time.…”

Section: Introductionmentioning

confidence: 99%

“…To the best of our knowledge, except [9] and [22], no other published benchmark results for EX-SOPs are available. Exact minimization algorithms for EX-SOPs with up to five variables were shown in [5,7]. Recently, we developed algorithms to obtain optimal EX-SOPs for single-output six-variable functions [6].…”

Section: Introductionmentioning

confidence: 99%

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A heuristic algorithm to design AND-OR-EXOR three-level networks

Debnath

Sasao

Proceedings of 1998 Asia and South Pacific Design Automation Conference

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Abstract-An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products expressions (EX-SOP). In this paper, we show an algorithm to simplify EX-SOPs for multipleoutput functions. Our objective is to minimize the number of distinct products in the sum-of-products expressions of EX-SOPs. The algorithm uses a divide-and-conquer strategy. It recursively applies the Shannon decomposition on a function with more than five variables. The algorithm obtains EX-SOPs for the five-variable functions by using an exact minimization program, then combines those EX-SOPs to generate EX-SOPs for the functions with more variables. We present experimental results for a set of benchmark functions, and show that EX-SOPs require many fewer products and literals than sum-of-products expressions. This is evidence that AND-OR-EXOR is a powerful architecture to realize many practical logic functions. Index Terms-Three-level network, AND-EXOR, logic minimization, decomposition, programmable logic device.

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“…In the last few years significant progress in the minimization of EX-SOPs have been made [4,6,13]. Upper bounds on the number of products in EX-SOPs are reported [2,3,5]. AND-OR-EXOR network where the output EXOR gate have unlimited fan-in is considered [12].…”

Section: Introductionmentioning

confidence: 99%