Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders

Abstract

Debatosh DEBNATH †a) , Nonmember and Tsutomu SASAO † †b) , Member SUMMARY This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-ofproducts expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EXSOPs where some outputs of the function are minimized in the complemented form and presented techniques to minimize EX-SOPs for adders by using an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. The proposed algorithm produces solutions with a half products of AOXMINlike algorithm in 250 times shorter time for large adders with two-valued inputs. We also proved that an n-bit adder with two-valued inputs requires at most 3 · 2 n−2 + 7n − 5 products in an EX-SOP while it is known that a sum-of-products expression (SOP) requires 6 · 2 n − 4n − 5 products. key words: three-level network, logic minimization, adder, programmable logic IntroductionProgrammable logic arrays (PLAs) with two-input EXOR gates at the outputs, also known as AND-OR-EXOR PLAs ( Fig. 1) [28], are a powerful architecture to realize many logic functions. The AND-OR-EXOR PLA realizes an EXOR of two sum-of-products expressions (EX-SOP). Minimization of the number of products in EXSOPs is an important step in the optimization of AND-OR-EXOR PLAs, because the number of products is directly related to the cost of PLAs. EX-SOPs are promising because, for many practical logic functions, they often require many fewer products than sum-of-products expressions (SOPs) [7], [10], [11], [15], [16], [28].AND-OR-EXOR three-level networks are suitable for implementing adders, which serve as building blocks for synthesizing many other arithmetic circuits [21]. For example, Texas Instruments' SN181 arithmetic circuit and SN283 four-bit adder have two-input EXOR gates in the outputs [31]; Monolithic Memories' ZHAL20X8A eight-bit counter realizes EX-SOPs [19]. An AND-OR-EXOR is one of the simplest three-level architecture, since it contains only a single two-input EXOR gate. However, its logic capabil- ity is quite high. Because of this, various programmable logic devices (PLDs) with two-input EXOR gates in the outputs were developed. Important contributions of the paper are as follows:• We present a method to reduce the number of products in EX-SOPs by considering output phase optimization [26], where some components of the function are implemented in the complemented form.• We develop a heuristic method to minimize EX-SOPs for adders with two-and four-valued inputs by using an extension of the AOXMIN algorithm [10].• We proved that an n-bit adder with two-valued inputs requires at most 3·2 n−2 +7n−5 products in an EX-SOP.A crucial step in AOXMIN is to partition the products of an SOP of the given function into two sets, which is done by a random method. We propose a partitioning method for adders. Our experimental result demonstrates that, for an n-bit adder w...

Dimension-reducible Boolean functions based on affine spaces

“…After the testing phase, we represent χ A using its CEX, getting an EXOR-AND network, and we then minimize f A in SOP form [Brayton et al 1984;Coudert 1995]. (Observe that f A can be synthesized in any logical framework, e.g., in threelevel-logic form [Debnath and Sasao 1997a;1997b;1998;Dubrova et al 1995;1999;Perkowski 1995;Sasao 1995].) The synthesis of f A could be easier than the synthesis of f , since f A depends on dim A < n variables.…”

A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks

“…For example, Texas Instruments' SN74LS181 arithmetic logic unit has EXOR gates in the outputs [24]. Programmable logic arrays (PLAs) with two-input EXOR gates in the outputs efficiently realize adders [5], [25].…”