A heuristic algorithm to design AND-OR-EXOR three-level networks

Abstract

Abstract-An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products expressions (EX-SOP). In this paper, we show an algorithm to simplify EX-SOPs for multipleoutput functions. Our objective is to minimize the number of distinct products in the sum-of-products expressions of EX-SOPs. The algorithm uses a divide-and-conquer strategy. It recursively applies the Shannon decomposition on a function with more than five variables. The algorithm obtains EX-SOPs for the five-variable functions by using an exact minimization program, then combines those EX-SOPs to generate EX-SOPs for the functions with more variables. We present experimental results for a set of benchmark functions, and show that EX-SOPs require many fewer products and literals than sum-of-products expressions. This is evidence that AND-OR-EXOR is a powerful architecture to realize many practical logic functions. Index Terms-Three-level network, AND-EXOR, logic minimization, decomposition, programmable logic device.

Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders

“…AND-OR-EXOR networks where output EXOR gates have unlimited fan-in is considered [27]. During the last several years significant progress in the heuristic minimization of EX-SOPs have been made and many interesting results are reported [7], [10], [11], [15], [16], [28]. However, no efficient algorithm to design AND-OR-EXOR PLAs for adders is developed.…”

“…Minimization of the number of products in EXSOPs is an important step in the optimization of AND-OR-EXOR PLAs, because the number of products is directly related to the cost of PLAs. EX-SOPs are promising because, for many practical logic functions, they often require many fewer products than sum-of-products expressions (SOPs) [7], [10], [11], [15], [16], [28].…”

“…Minimization of the number of products in EXSOPs is an important step in the optimization of AND-OR-EXOR PLAs, because the number of products is directly related to the cost of PLAs. EX-SOPs are promising because, for many practical logic functions, they often require many fewer products than sum-of-products expressions (SOPs) [7], [10], [11], [15], [16], [28].AND-OR-EXOR three-level networks are suitable for implementing adders, which serve as building blocks for synthesizing many other arithmetic circuits [21]. For example, Texas Instruments' SN181 arithmetic circuit and SN283 four-bit adder have two-input EXOR gates in the outputs [31]; Monolithic Memories' ZHAL20X8A eight-bit counter realizes EX-SOPs [19].…”

Multiple-valued minimization to optimize PLAs with output EXOR gates

“…Design methods for adders by using AND-OR-EXOR PLAs with more than one-bit decoders were developed at IBM [15]. In the last few years significant progress in the minimization of EX-SOPs have been made [4,6,13]. Upper bounds on the number of products in EX-SOPs are reported [2,3,5].…”

“…Minimization of the number of products in EX-SOPs is an important step in the optimization of AND-OR-EXOR PLAs, because the number of products is directly related to the cost of PLAs. EX-SOPs are promising because, for many practical logic functions, they often require many fewer products than sum-of-products expressions (SOPs) [4,6,13].…”