An Investigation on Border Traps in III–V MOSFETs With an In_0.53Ga_0.47As Channel

Abstract

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristic are poorly understood at present. In this work, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origin. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modelling and device time-to-failure projection.

Schottky Junction Vertical Channel GaN Static Induction Transistor with a Sub‐Micrometer Fin Width

“…Vertical channel topology also allows GaN transistors to enhance their properties in blocking electric field, surface state‐related dispersion, and current density, increasing long‐term stability and reliability as well as area and cost effectiveness . GaN has been successfully fabricated so far into various forms of vertical transistors such as metal–oxide–semiconductor (MOS) field effect transistor (FET), in‐situ oxide, GaN interlayer‐based vertical trench MOSFET (OG‐FET), current aperture vertical electron transistor (CAVET), and junction FET . However, the difficulty in the activation of p ‐type GaN to realize a reliable p – n junction and dielectric‐related threshold voltage shift or dispersion still remain as challenges .…”

Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

“…Electrical characterization was performed on patterned wafers using a Keysight B1500A semiconductor analyzer. The tested devices with a channel length of 500 nm and 4800 fins were used for the charge pumping (CP) measurement and direct-current current voltage (DCIV) measurements, whereas devices with a channel length of 500 nm and 32 fins were used for measuring the time kinetics of the threshold voltage shift (ΔV T ) and for multi-level discharging-based multi-pulse energy profiling (Multi-DMP) measurement [13,14].…”

As-grown-Generation Model for Positive Bias Temperature Instability

“…AT dominates initially, while EAD follows a power law. Further details can be found from our early works [26,27]. The kinetics for EAD and AT under different overdrive voltages are extracted and shown in Figs.8a&b, respectively.…”

“…a). The discharge profiles of pre-existing traps using the method in ref26. The traps were first charged under Vgch=Vg-Vth=0.3 V and the subsequent discharging was recorded to give the lowest set of symbols.…”