Schottky Junction Vertical Channel GaN Static Induction Transistor with a Sub‐Micrometer Fin Width

Abstract

GaN‐based vertical transistors have demonstrated its excellent properties for high‐power and high‐frequency electronic devices. This work introduces a GaN‐based static induction transistor (SIT) which is another form of vertical GaN transistors without requiring any p‐type GaN and gate dielectrics for its operation. Processing strategy to generate the GaN SIT with a sub‐micrometer fin width involves photoresist (PR)‐assisted planarization with an understanding of dry etch parameters for the planar PR surface. The efficacy of this process is demonstrated by the device's triode‐like output characteristics with high current density (0.65 kA cm−2) and low ON resistance (1.48 mΩ cm2) at 1 V of drain voltage. In addition, the electrical properties such as current density and modulation are examined depending on the fin width of GaN SIT. The result reveals that the size reduction in the GaN SIT utilizing the sub‐micrometer fin as a channel could increase the current modulation, but it could decrease the current density because of the raised potential minima due to the depletion region overlap. It is believed that the GaN SIT demonstrating high blocking voltage and low ON resistance would present a very promising class of transistor for next‐generation high‐power and high‐frequency electronics.

A Study on the First‐Derivative Output Properties of GaN Static Induction Transistor with Submicrometer Fin Width

“…This result is comparable with a recent report on GaN vertical fin FETs . The decrease in J d with shortening of the fin width was described in our previous report and briefly reiterated here. Decreasing the fin width to the submicrometer size causes merging of depletion regions, which are induced by Schottky‐gate contact on each side of the fin, resulting in raising the potential minima, generally called saddle point, in the channel.…”

“…Then, the SiO 2 dielectric layer to lower the leakage current between the gate metal extension and c ‐plane of GaN was deposited by plasma‐enhanced chemical vapor deposition (PECVD). The SiO 2 dielectric layer was etched out from the top and sidewall of fin through the PR‐assisted planarization process, of which details can be found in the previous study . In the PR‐assisted planarization process, PR etching was an important step to even out the etched PR surface without any PR residues, which could induce unwanted micromasking during the subsequent SiO 2 etching.…”

“…Recently, our group demonstrated Schottky‐barrier GaN SITs using a self‐aligned process along with a photoresist (PR)‐assisted planarization technique . This approach enabled the fabrication of a submicrometer fin structure in a recess‐gate configuration and the examination of various performances, such as current density and modulation dependence on the size of fin width, which enhanced our understanding of the fundamental properties of the GaN SIT with a submicrometer channel.…”

Design of High I on/I off Fin-Statistic Induction Transistor Based on Gallium Nitride

“…When the device is subjected to different gate voltage conditions, the withstand voltage of the SIT designed in this paper reaches 830 V at different gate voltages, giving full play to the high withstand voltage advantage of GaN material. Compared with the SIT with a breakdown voltage of 160 V in [8], it means that the SIT in this paper can be applied to more extreme conditions.…”

“…In 2019, Chun, Jaeyi, et al designed a Schottky junction vertical channel GaN electrostatic induction transistor with I on /I off reached 10 3 level. The breakdown voltage was 160 V [8] . In the same year, Matthew Hartensveld et al fabricated a vertical channel nanowire GaN SIT with I on /I off of 2×10 6 [9] .…”