An investigation of species dependence in germanium pre-amorphized and laser thermal annealed ultra-shallow abrupt junctions

Highly phosphorus-doped silicon source/drains are investigated to improve the performance of N-type metal-oxide-semiconductor field-effect transistors by decreasing their resistance and imparting strain to their channels. To find effective high temperature annealing for the activation of phosphorus in the source/drains, we apply single- and multi-pulse nanosecond laser annealing on highly phosphorus-doped silicon. The microstructure, strain, and electrical properties of highly phosphorus-doped silicon before and after laser annealing are analyzed. Our results demonstrate that the defects in both the recrystallized silicon and the end of range are decreased with 600 mJ cm−2 10-pulse annealing while considerable increase in phosphorus activation is achieved.

Section: Introductionmentioning

confidence: 99%

Recrystallization and activation of ultra-high-dose phosphorus-implanted silicon using multi-pulse nanosecond laser annealing

Lee

Ryu

Park

et al. 2020

“…We currently rule out SPE due to the large leakage current by residual defects. [1][2][3][4][5][6][7]…”

Section: Introductionmentioning

confidence: 99%

Ultra-Shallow Junction Formation by Non-Melt Laser Spike Annealing and its Application to Complementary Metal Oxide Semiconductor Devices in 65-nm Node

Shima¹,

Hiraiwa²

2006

We activated source/drain junctions of complementary metal oxide semiconductor (CMOS) by simply replacing rapid thermal annealing (RTA) in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers, unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better V th roll-offs and larger drain currents compared to those formed by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

“…Such a film acts as a heat source over which the heat is distributed uniformly, preserving the physical integrity of structures such as polycrystalline silicon gate electrodes on the Si wafer. 3,4) In addition, dopant profiles can be finely controlled by controlling the preamorphization depth that is formed by heavy ion implantation. 5) This is based on the fact that the melting to recrystallization can be induced selectively in the amorphous Si by laser annealing under appropriate laser-power conditions because amorphous Si melts at a temperature lower than that needed to melt single-crystal Si.…”

Section: Introductionmentioning

confidence: 99%

Realization of Low CoSi₂/p⁺-Silicon Contact Resistance with Low Junction Leakage Current and Junction Capacitance Using Laser Thermal Process

Yamamoto

Kubo

Wang³

et al. 2005

In this paper we report source–drain engineering for the realization of low contact resistance between CoSi2 and p+ Si with low junction leakage current and low junction capacitance using laser thermal processing (LTP) and the optimization of ion implantation conditions. We first demonstrate the impact of pre-amorphization on the reduction of the contact resistivity of a CoSi2/p+ deep source–drain (deep-SD) interface using laser thermal processing (LTP). A highly activated dopant profile at the CoSi2/deep-SD interface is required to reduce the contact resistivity there. Dopant profile can be finely controlled by implanting heavy ions to preamorphize a region to the desired depth and then using an appropriate laser power to selectively melt the amorphous Si, which has a melting temperature lower than that of single-crystal Si. We can thus form a highly activated boxlike dopant profile suitable for a deep-SD by using LTP and relatively deep preamorphization. Then, we discuss how to suppress the leakage current and the capacitance of the junctions. The larger junction capacitance and junction leakage current due to the abrupt deep-SD profile can be greatly reduced by combining LTP with lower-dose, higher-energy implantation and RTA prior to preamorphization (predoping and pre-RTA) to form a graded deep-SD profile beyond the abrupt deep-SD profile and overwhelm the channel doping profile, resulting in a wide depletion layer.