We activated source/drain junctions of complementary metal oxide semiconductor (CMOS) by simply replacing rapid thermal annealing (RTA) in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers, unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better V th roll-offs and larger drain currents compared to those formed by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

A three-dimensional (3-D) vertical chain-cell-type phase-change memory (VCCPCM) for next-generation large-capacity storage was developed. The VCCPCM features formation of memory holes in multi-layered stacked gates by using a single mask and a memory array without a selection transistor. As a result of this configuration, the number of process steps for fabricating the VCCPCM is reduced. The excellent scalability of the VCCPCM's new phase-change material makes it possible to reduce the cell size beyond the scaling limit of flash memory. In addition, a poly-silicon selection diode makes it possible to reduce the cell factor to 4F 2 . Consequently, relative cost of the VCCPCM compared to 3-D flash memory is reduced to 0.2. IntroductionThe most important requirement for the storage-memory market is reduction of bit cost, and that requirement has been met by reducing the cell size of flash memory. However, high-voltage operation of flash memory makes it difficult to further reduce cell size. It has recently been reported that the bit-cost reduction can be continued by utilizing 3-D flash memory [1]. 3-D flash memory needs fewer process steps compared to simple stacking of flash memory, but reducing cell size is difficult for two reasons. Firstly, a 20-nm-thick ONO layer in the memory hole is needed and, secondly, a vertical poly-silicon selection MOS transistor needs a cell factor of 6F 2 [1]. In this work, a vertical chain-cell-type phase-change memory (VCCPCM), which can overcome these problems concerning 3-D flash in view of bit cost, is proposed. The key technologies of this VCCPCM are (1) a vertical chain cell for reducing the number of process steps, (2) a scalable new phase-change material for reducing cell size, and (3) a poly-Si XY-selection diode for reducing cell factor to 4F 2 . A poly-Si diode [2] and a lateral chain-cell-type PCM [3] were previously developed. Relative bit cost of both 3-D flash memory and VCCPCM is shown in Fig. 1. By virtue of technologies (1) to (3), the relative bit cost of the VCCPCM compared to 3-D flash memory is reduced to 0.2. Table 1 compares characteristics of 3-D flash memory and VCCPCM. In the present study, set, reset, and reading operations of the VCCPCM were confirmed. Moreover, off-current variation of the poly-Si diode was suppressed by short-time annealing.2. Device structure and operation method The structure of the VCCPCM is shown in Fig. 2. The poly-Si selection diode and VCCPCM are connected serially and positioned at the cross points between the bit and word lines. The structure and equivalent circuit of a VCCPCM are shown in Fig. 3. The gate oxide, channel poly-silicon, and the phase-change material are formed on the side of the holes in the stacked gates. Each memory cell consists of a poly-silicon transistor and a phase-change layer connected in parallel. The memory cells are connected serially in the vertical direction. In the set/reset operations, an off-voltage is applied to the gate at the selected cell, and a positive on-voltage is applied to the unselect...

Approach to the characterization of through-oxide boron implantation by secondary ion mass spectrometryWe have quantitatively investigated how boron segregates to regions close to the surface, and what controls this phenomenon, using x-ray photoelectron spectroscopy, Fourier transform infrared spectroscopy and backside secondary ion mass spectrometry measurement techniques. We found that, contrary to the equilibrium segregation, the pileup of boron is mainly on and within 0.6 nm of the Si side of the interface, and that there is no difference between the kind of encapsulation. This also suggests that the pileup of boron is mainly on the Si side, and implies that the main factor in this segregation is the existence of the Si surface. From the viewpoint of device fabrication, this result seems to be useful in terms of the fabrication of sidewalls. The possibility of boron pileup to occurring in the interstitial state was also shown. Our results suggested a way of looking at dopant profiles by predictive computer modeling.

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Thin drift layers were used to realize n-channel 4H-SiC IGBTs with an extremely low switching loss. The thickness of a drift layer was 60 μm, which was designed for a blocking voltage of 6.5 kV. An on-voltage of 5.4 V was obtained at a collector current of 100 A/cm2 and the specific differential on-resistance at 100 A/cm2 was 20 mΩcm2 at room temperature, indicating proper bipolar operation. A switching evaluation of the SiC IGBTs was performed with a bus voltage of 3.6 kV and a load current of 10 A, and a turn-off loss of 1.2 mJ was obtained. This turn-off loss is very small compared to the values in the current literatures, and was estimated to be an over 80% reduction. The series operation of thin-drift-layer 6.5 kV SiC IGBTs can ensure a lower switching loss than the single operation of higher blocking voltage devices in power conversion systems.