Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS

Shima, Akio; Wang, Yun; Talwar, S.; Hiraiwa, Atsushi

doi:10.1109/vlsit.2004.1345463

Cited by 35 publications

(21 citation statements)

References 2 publications

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“…Figure 5.1 shows that cluster implantation can produce very shallow, abrupt asimplanted doping profiles, but conventional spike annealing induces significant dopant diffusion and leads to much deeper junction depth [89] . The milli-second annealing (MSA) using xenon lamp or LASER for annealing is reported with much less diffusion yet still achieving high electrical activation [90,91] instead of the spike annealing process. The performance enhancement is very sensitive to peak MSA temperature.…”

Section: Source/drain Engineeringmentioning

confidence: 99%

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Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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Section: Source/drain Engineeringmentioning

confidence: 99%

“…Three major MSA applications have been demonstrated. One is the MSA-only approach [92] , and the second is a combination of spike-RTA followed by MSA (MSA is implemented after spike-RTA to assist dopant activation) [93] . The third one is that MSA is implemented prior to spike-RTA to modulate the junction profile [94] .…”

Section: Source/drain Engineeringmentioning

confidence: 99%

Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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“…Initially, standard B and BF 2 implants were used to emulate devices' Source/Drain (S/D) and comparison with spike and laser annealing [4] was performed as presented in a two times decrease in junction depth. Flash annealing at low preheat temperatures showed comparable activation to laser; but the combination of spike anneal and flash achieves higher dopant activation at shallower junctions with junction depths down to 10 nm.…”

Section: Characterizing Flash Annealingmentioning

confidence: 99%

Millisecond flash annealing: Applications for USJ formation and optimization of device electrical characteristics

Foggiato¹,

Yoo²

2005

Materials Science and Engineering: B

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“…Millisecond Anneal (MSA) technology, namely, Laser Spike Annealing (LSA) [2,3] or Flash Lamp Annealing (FLA) [4,5], is one of the promising candidates. However, it has been revealed that it is difficult to achieve the ITRS [1] target for 45 nm node (hp65 nm node) by conventional anneal technologies.…”

Section: Introductionmentioning

confidence: 99%

Issues and Optimization of Millisecond Anneal Process for 45 nm node and beyond

et al. 2006

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We have investigated MSA, namely, Laser Spike Annealing (LSA) and Flash Lamp Annealing (FLA), dopant activation technology of source/drain extension for 45 nm node, which can be substituted for spike RTA. Since it is possible to achieve a similar relation between a sheet resistance and a junction depth by using either FLA or LSA, both annealing methods are capable of providing the junction characteristics required by the ITRS target. However, we have noticed that there are three crucial issues from the viewpoints of device integration and CMOSFET performance: junction leakage current, gate leakage current and pattern dependence. In this paper, we discuss these issues and indicate how to cope with them.

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Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS

Cited by 35 publications

References 2 publications

Challenges of 22 nm and beyond CMOS technology

Challenges of 22 nm and beyond CMOS technology

Millisecond flash annealing: Applications for USJ formation and optimization of device electrical characteristics

Issues and Optimization of Millisecond Anneal Process for 45 nm node and beyond

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