Realization of Low CoSi₂/p⁺-Silicon Contact Resistance with Low Junction Leakage Current and Junction Capacitance Using Laser Thermal Process

Abstract

In this paper we report source–drain engineering for the realization of low contact resistance between CoSi2 and p+ Si with low junction leakage current and low junction capacitance using laser thermal processing (LTP) and the optimization of ion implantation conditions. We first demonstrate the impact of pre-amorphization on the reduction of the contact resistivity of a CoSi2/p+ deep source–drain (deep-SD) interface using laser thermal processing (LTP). A highly activated dopant profile at the CoSi2/deep-SD interface is required to reduce the contact resistivity there. Dopant profile can be finely controlled by implanting heavy ions to preamorphize a region to the desired depth and then using an appropriate laser power to selectively melt the amorphous Si, which has a melting temperature lower than that of single-crystal Si. We can thus form a highly activated boxlike dopant profile suitable for a deep-SD by using LTP and relatively deep preamorphization. Then, we discuss how to suppress the leakage current and the capacitance of the junctions. The larger junction capacitance and junction leakage current due to the abrupt deep-SD profile can be greatly reduced by combining LTP with lower-dose, higher-energy implantation and RTA prior to preamorphization (predoping and pre-RTA) to form a graded deep-SD profile beyond the abrupt deep-SD profile and overwhelm the channel doping profile, resulting in a wide depletion layer.