An investigation of EUV lithography defectivity

Cummings, K. D.; Laursen, Thomas; Pierson, Bill; Han, Sang-In; Watso, Robert; Dommelen, Youri van; Lee, Brian; Deng, Yunfei; Fontaine, Bruno La; Wallow, Thomas I.; Okoroanyanwu, U.; Wood, O. R.; Tchikoulaeva, Anna; Holfeld, Christian; Peters, Jan Hendrick; Koay, Chiew-Seng; Petrillo, Karen; DiBiase, Tony; Kini, Sumanth; Mizuno, Hiroyuki

doi:10.1117/12.801528

Cited by 7 publications

(2 citation statements)

References 7 publications

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“…The first ever EUV device integration demonstration was carried out using the EUV Alpha Demo Tool in Albany to pattern the first interconnect level on 45nm test chips 1 manufactured at AMD's fabrication facility in Dresden, Germany. Die-to-die inspection of wafers printed with the EUV device integration mask showed many fewer repeating (mask related) defects than expected given the defect density of the mask blank 2 . The quality of resist images printed with the EUV Alpha Demo Tool in many cases exceeds those that can be printed with 193 nm immersion lithography.…”

Section: Introductionmentioning

confidence: 73%

Integration of EUV lithography in the fabrication of 22-nm node devices

Wood

Koay

Petrillo

et al. 2009

Alternative Lithographic Technologies

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On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and below, we are testing its integration into standard semiconductor process flows for 22 nm node devices.In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography; the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination.The patterned integration wafers have been processed through metal deposition and polish at the contact level and are now being patterned at the first interconnect level.

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Section: Introductionmentioning

confidence: 73%

Integration of EUV lithography in the fabrication of 22-nm node devices

Wood

Koay

Petrillo

et al. 2009

Alternative Lithographic Technologies

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“…However, for the demonstration product type used, the inspection sensitivities were appropriate. This work was extended in 2008 to look at sub-50 nm hp DRAM and logic designs with the latest tool and pixel sizes, as well as extension to EUV [6]. In all cases, repeating defects located on the wafer print could easily be found on the mask and classified using SEM.…”

Section: Defectivitymentioning

confidence: 99%

Optimal mask characterization by Surrogate Wafer Print (SWaP) method

Kimmel

Hoellein

Peters

et al. 2008

Photomask Technology 2008

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Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask relative to the specifications is done completely by the mask maker. As the challenges of low-k 1 imaging continue to grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers' continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore, improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent and compelling. The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images, rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance, which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab mask qualification to validate defect and dimensional performance. In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is not only feasible, but, in some cases, desirable. This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an enhancement to mask characterization quality including defectivity, dimensional control, pattern fidelity, and in-plane distortion. We present a thorough analysis of both the technical and logistical challenges coupled with an objective view of the advantages and disadvantages from both the technical and financial perspectives. The analysis and model used by the AMTC will serve to provoke other mask shops to prepare their own analyses then consider this new paradigm for mask characterization and qualification.

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