An experimental 4 Mb CMOS EEPROM with a NAND structured cell

Itoh,; Momodomi,; Shirota,; Iwata,; Nakayama,; Kirisawa,; Tanaka, M.; Toita,; Inoue,; Masuoka,

doi:10.1109/isscc.1989.48209

Cited by 27 publications

(4 citation statements)

References 1 publication

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“…Thus, the electron concentration of the channel decreases due to the occurrence of HCI phenomenon. [25][26][27][28][29][30]…”

Section: Hci Phenomenon Due To Excessive Nlsb Effectmentioning

confidence: 99%

Optimal dummy word line condition to suppress hot carrier injection phenomenon due to the natural local self-boosting effect in 3D NAND flash memory

Jeong¹,

Ham²,

Han³

et al. 2020

Jpn. J. Appl. Phys.

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The main cell channel in 3D NAND flash structures easily goes into the floating state, because it is not directly connected to the substrate, resulting in the down-coupling phenomenon (DCP). As DCP reduces the boosting potential of the inhibit string during the program and verify operations, the natural local self-boosting (NLSB) effect is reduced, which in turn reduces the channel potential and causes a program disturb. However, if the channel potential of the selected word line (WL) is significantly increased by excessive NLSB, a hot carrier injection (HCI) occurs due to the potential difference between the adjacent WLs, even at a low channel potential. Therefore, we introduced a dummy WL to reduce HCI.

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“…Thus, the electron concentration of the channel decreases due to the occurrence of HCI phenomenon. [25][26][27][28][29][30]…”

Section: Hci Phenomenon Due To Excessive Nlsb Effectmentioning

confidence: 99%

Optimal dummy word line condition to suppress hot carrier injection phenomenon due to the natural local self-boosting effect in 3D NAND flash memory

Jeong¹,

Ham²,

Han³

et al. 2020

Jpn. J. Appl. Phys.

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“…Error correction codes (ECCs) are widely used to ensure the reliability of NAND flash memory. Hamming codes [27], RS codes [28], BCH codes [29] and LDPC codes are used to meet the demand of error correction capability. LDPC codes have comparably stronger error correction capability.…”

Section: B Error Correctionmentioning

confidence: 99%

CeSR + Assisted LDPC: A Holistic Strategy to Improve MLC NAND Flash Reliability

et al. 2020

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NAND flash suffers from program interference and retention errors, which negatively affect its reliability. Existing schemes preprocess raw data before writing them to reduce Raw Bit Error Rate (RBER) and leverage ECCs (such as LDPC codes) to reduce Uncorrectable Bit Error Rate (UBER). Prior arts failed to take into account the counteractions between the program interference and retention errors.Thus, they may lead to sub-optimal error avoidance. Besides, after the preprocessing procedure, data randomness may be affected. Since NAND flash shows numerical-correlated error characteristics, there's a potential to provide such information to LDPC codes to further improve performance. In this article, we propose a holistic strategy consisting of two coupled procedures to enhance flash reliability. First, we use our previously proposed CeSR strategy to reduce RBER. Second, we improve the existing LDPC codes and name it Assisted LDPC strategy to reduce UBER. The Assisted LDPC is deeply coupled with CeSR. It leverages the data pattern after CeSR to improve the decoding success rate and accelerate the decoding procedure. The evaluation shows that compared with the state-of-the-art NRC strategy, CeSR can reduce the RBER of hot and cold data by up to 20.30% and 85.13%, respectively. Besides, compared with the traditional LDPC, the Assisted LDPC decoding strategy can increase the decoding success rate by up to 97% for cold data and reduce the average decoding iteration number of MSB pages for hot and cold data by up to 31.6% and 73.9%, respectively. INDEX TERMS Cell state remapping, flash reliability, LDPC codes, NAND flash memory, program interference, retention error.

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“…Table 1 represents the set of parameters used in our cloud framework. Let's assume that our Big Data set over time has a Poisson error arrival rate in memory of λ bit errors sec 512 bytes ⁄ ⁄ [13]. Let's define the optimum effective bandwidth of cloud reconstruction of the Big Data set,6, as the value T 789 that enables D to be 1% of T 789 STEP 1: For a given and Big Data size, 6, we determine the optimum Map-Reduce parallelism P. Based upon and the size of 6, divide the set 6 into 6 /P memories.…”

Section: System Model For Big Data Reconstructionmentioning

confidence: 99%

A fast map-reduce algorithm for burst errors in big data cloud storage

Qin

Kelley

Saedy

2015

2015 10th System of Systems Engineering Conference (SoSE)

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In distributed storage for Big Data systems, there is a need for exact repair, high bandwidth codes. The challenge for exact repair in big-data storage is to simultaneously enable both very high bandwidth repair using Map-Reduce and simple coding schemes that also combine robust maximally distance separable (MDS) exact repair. MDS repair is for the rare, but exceptional outlier error patterns requiring optimum erasure code reconstruction. We construct the optimum fast bandwidth repair for big-data sources. Our system uses Map-Reduce, exact repair reconstruction. The algorithm combines MDS with a second fast decode algorithm in a cloud environment. We illustrate cloud experiments for optimum fast bandwidth reconstruction for 1-Exabyte Big Data in the cloud and demonstrate cloud results for Poisson error rate arrival models. Unlike prior methods, we jointly solve the problem of fast bandwidth repair for burst-memory error patterns and for code rates up to in a real time error model framework for Big Data. Furthermore, simulations indicate this method outperforms prior fast bandwidth approaches for burst errors. We also illustrate Map-Reduce algorithm optimized for fast bandwidth repair in Big Data storage in clouds.

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An experimental 4 Mb CMOS EEPROM with a NAND structured cell

Cited by 27 publications

References 1 publication

Optimal dummy word line condition to suppress hot carrier injection phenomenon due to the natural local self-boosting effect in 3D NAND flash memory

Optimal dummy word line condition to suppress hot carrier injection phenomenon due to the natural local self-boosting effect in 3D NAND flash memory

CeSR + Assisted LDPC: A Holistic Strategy to Improve MLC NAND Flash Reliability

A fast map-reduce algorithm for burst errors in big data cloud storage

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