Optimal dummy word line condition to suppress hot carrier injection phenomenon due to the natural local self-boosting effect in 3D NAND flash memory

Abstract

The main cell channel in 3D NAND flash structures easily goes into the floating state, because it is not directly connected to the substrate, resulting in the down-coupling phenomenon (DCP). As DCP reduces the boosting potential of the inhibit string during the program and verify operations, the natural local self-boosting (NLSB) effect is reduced, which in turn reduces the channel potential and causes a program disturb. However, if the channel potential of the selected word line (WL) is significantly increased by excessive NLSB, a hot carrier injection (HCI) occurs due to the potential difference between the adjacent WLs, even at a low channel potential. Therefore, we introduced a dummy WL to reduce HCI.

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

“…In addition, to reduce the trap-assisted BTBT current generated by grain boundary trap, a method of arranging a dummy WL bias between the select transistor and the main cell during program operation was proposed [12,25]. By gradually adjusting their pass voltage during program operation, program disturbances caused by HCI were also reduced.…”

Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location

“…Figure 1 also shows that the boosting potential of WL0 is the largest, which leads to a further drop in the electron concentration of WL0, which is relatively less than that of the other WL. Therefore, the high boosting potential of edge WL resulted in the HCI phenomenon, which reduced the electron concentration [9]. Figure 6 shows the analysis of NLSB by WL when DWL is present in 3D NAND.…”

“…In order to control such program disturbance, it is necessary to further study the NLSB generated for each WL. Moreover, the maximum potential boosting of NLSB at an edge WL can cause secondary problems such as hot carrier injection (HCI) [9]. Previous studies analyzed how the NLSB phenomenon occurs when the bias applied to the selected WL or the pattern of adjacent cells changes [10][11][12][13].…”

Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory

“…When the program/erase cycle is increased, the reliability of the device decreases due to various problems, such as the deterioration of the retention characteristics caused by the heat that is generated during the P/E operation, cell disturbance caused by the P/E operation, and the deterioration of the durability of the blocking oxide [11][12][13][14][15][16][17]. This problem can be improved by using a dummy WL to split the blocks and to erase only the selected blocks [18][19][20][21]. In this case, the bias condition of the dummy WL affects the neighboring cells, because the bias that is applied to the dummy WL affects the channel potential according to the coupling ratio of the gate dielectrics [22][23][24][25].…”