An efficient approach to simultaneous transistor and interconnect sizing

Abstract

In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We dene a class of optimization problems as CH-posynomial programs and reveal a general dominance property for all CH-posynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CH-posynomial programs and propose an ecient and near-optimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buer and wire sizing problem for real designs, it reduces the maximum delay b y u p t o 16.1%, and more signicantly, reduces the power consumption by a factor of 1.63x, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth area-delay trade-o. Moreover, the algorithm optimizes a clock net of 367 drivers/buers and 59304m-long wire in 120 seconds, and a 32bit adder with 1,026 transistors in 66 seconds on a SPARC-5 workstation.