Timing optimization for multisource nets: characterization and optimal repeater insertion

Lillis, John; Cheng, Chung‐Kuan

doi:10.1109/43.748162

Cited by 18 publications

(5 citation statements)

References 21 publications

(31 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To deal with this trend, many helpful researches, such as timing models [4,5], timing-driven Steiner tree algorithms [6,7], and interconnect design algorithms considering buffer insertion or/and wire sizing [8][9][10], have been done to reduce interconnect delay. These researches mainly focus on single net routing.…”

Section: Introductionmentioning

confidence: 99%

Utaco

Tong

Hong

Bao

et al. 2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

View full text Add to dashboard Cite

Timing performance and routability are two main issues of global routing. In this paper, we adopt a shadow price mechanism to incorporate the two issues into one unified objective function. The shadow price of a net is the sum of its congestion price and timing price. Based on the new formulation, this paper presents the UTACO algorithm for standard cell (SC) global routing. The experimental results show that UTACO is efficient for both timing and congestion optimization.

show abstract

Section: Introductionmentioning

confidence: 99%

Utaco

Tong

Hong

Bao

et al. 2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

View full text Add to dashboard Cite

show abstract

“…Recently, bidirectional onchip global interconnecting subsystems have also been studied quite extensively for supporting electronic design automation of system-on-chip platforms [82][83][84][85]. Hence, physical layer design of an NoC channel to support bidirectional data transmission should be of little difficulty.…”

Section: Design Requirementsmentioning

confidence: 99%

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2011

Journal of Electrical and Computer Engineering

View full text Add to dashboard Cite

The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

show abstract

“…1(e). Notice that it is generally difficult to buffer tri-state buses [16], which might be necessary to maintain reasonable slew rates if these buses are routed over long distances.…”

Section: B Read Logicmentioning

confidence: 99%

Benchmarking of Standard-Cell Based Memories in the Sub-$V_{\rm T}$ Domain in 65-nm CMOS Technology

Meinerzhagen

Sherazi

Burg

et al. 2011

IEEE J. Emerg. Sel. Topics Circuits Syst.

View full text Add to dashboard Cite

Abstract-In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-V T SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-V T domain of various SCM architectures are evaluated by means of a gate-level sub-V T characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-V T SRAM designs.

show abstract

Timing optimization for multisource nets: characterization and optimal repeater insertion

Cited by 18 publications

References 21 publications

Utaco

Utaco

Networks on Chips: Structure and Design Methodologies

Benchmarking of Standard-Cell Based Memories in the Sub-$V_{\rm T}$ Domain in 65-nm CMOS Technology

Contact Info

Product

Resources

About