An effective hybrid transactional memory system with strong isolation guarantees

Minh, Chi Cao; Trautmann, Martin; Chung, JaeWoong; McDonald, Austen; Bronson, Nathan; Casper, Jared; Kozyrakis, Christos; Olukotun, Kunle

doi:10.1145/1273440.1250673

Cited by 46 publications

(83 citation statements)

References 27 publications

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“…One promising approach is to use signatures, data structures that can represent an unbounded number of elements approximately in a bounded amount of state. Led by Bulk [7], several systems including LogTM-SE [31], BulkSC [8], and SigTM [17], have implemented read/write sets with per-thread hardware signatures built with Bloom filters [2]. These systems track the addresses read/written in a transaction by inserting them into the read/write signatures, and clear both signatures as the transaction commits or aborts.…”

Section: Introductionmentioning

confidence: 99%

Implementing Signatures for Transactional Memory

Sánchez¹,

Yen²,

Hill³

et al. 2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

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Transactional Memory (TM) systems must track the read and write sets-items read and written during a transaction-to detect conflicts among concurrent transactions. Several TMs use signatures, which summarize unbounded read/write sets in bounded hardware at a performance cost of false positives (conflicts detected when none exists).This paper examines different organizations to achieve hardware-efficient and accurate TM signatures. First, we find that implementing each signature with a single k-hashfunction Bloom filter (True Bloom signature) is inefficient, as it requires multi-ported SRAMs. Instead, we advocate using k single-hash-function Bloom filters in parallel (Parallel Bloom signature), using area-efficient single-ported SRAMs. Our formal analysis shows that both organizations perform equally well in theory and our simulationbased evaluation shows this to hold approximately in practice. We also show that by choosing high-quality hash functions we can achieve signature designs noticeably more accurate than the previously proposed implementations. Finally, we adapt Pagh and Rodler's cuckoo hashing to implement Cuckoo-Bloom signatures. While this representation does not support set intersection, it mitigates false positives for the common case of small read/write sets and performs like a Bloom filter for large sets.

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Section: Introductionmentioning

confidence: 99%

Implementing Signatures for Transactional Memory

Sánchez¹,

Yen²,

Hill³

et al. 2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

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show abstract

“…However, strong atomicity is more difficult to implement in software transactional memory systems. Most software transactional memory proposals so far have only supported weak atomicity, but recent work, e.g., [13,91,6,2], show how some of these short-comings can be addressed.…”

Section: Strong and Weak Atomicitymentioning

confidence: 99%

“…An alternative approach to implement unbounded transactional memory is to use signatures [14,15,103,13,87]. Signatures are data structures that can store the access information, i.e., addresses and read-/write-sets, for a thread in a compact form using Bloom filters [7].…”

Section: Signature-based Transactional Memorymentioning

confidence: 99%

“…One approach is to use hardware signatures to track the read-and write-sets of the transactions, as suggested in, e.g., SigTM [13] and FlexTM [92]. Further, Shriraman et al [92] suggest four hardware primitives to support high-performance and flexible software transactional memory implementations.…”

Section: Hardware Supported Software Transactional Memorymentioning

confidence: 99%

“…Signature-Accelerated Transactional Memory (SigTM) [13], is a hybrid transactional memory system that uses hardware signatures to track the read and write-sets for penging transactions. Conflict detection is also done in hardware, while all other TM functionality is done in software.…”

Section: Signature-accelerated Transactional Memory Sigtmmentioning

confidence: 99%

See 2 more Smart Citations

Transactional memory

Grahn¹

2010

Journal of Parallel and Distributed Computing

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Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip. In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task. Transactional memory tries to ease parallel program development by providing atomic and isolated execution of code sequences, enabling software composability and protected access to shared data. In addition, transactional memory has the ability to execute atomic code sequences in parallel as long as no data conflicts occur. Transactional memory implementation proposals exist for both hardware and software, as well as hybrid solutions. This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances the state-of-the-art in transactional memory research.

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Improving Performance by Reducing Aborts in Hardware Transactional Memory

Ansari

Khan

Luján

et al. 2010

High Performance Embedded Architectures and Compilers

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Abstract. The optimistic nature of Transactional Memory (TM) systems can lead to the concurrent execution of transactions that are later found to conflict. Conflicts degrade scalability, and may lead to aborts that increase wasted work, and degrade performance. A promising approach to reducing conflicts at runtime is dynamically, and transparently, reordering the execution of transactions upon discovery of conflicts. This approach has been explored in Software TMs (STMs), but not in Hardware TMs (HTMs). Furthermore, STM implementations of this approach cannot be ported to HTMs easily. This paper investigates the feasibility of such reordering in HTMs, and presents two designs that are scalable, independent of the on-chip interconnect, require only minor modifications to each core, and add no execution overhead if no conflicts occur. The evaluation takes LogTM-SE as a base line and considers benchmarks with different levels of contention (transactional conflicts). The results show that the preferred design increases HTM performance by up to 17% when contention is low, 57% when contention is high, and never degrades performance. Finally, the designs are orthogonal to LogTM-SE; they require no modification to cache structures, and continue to support transaction virtualization, open and closed unbounded nesting, paging, thread suspension, and thread migration.

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An effective hybrid transactional memory system with strong isolation guarantees

Cited by 46 publications

References 27 publications

Implementing Signatures for Transactional Memory

Implementing Signatures for Transactional Memory

Transactional memory

Improving Performance by Reducing Aborts in Hardware Transactional Memory

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