Collaboration between industry and academia supports improvement and innovation in industry and helps to ensure industrial relevance in academic research. This paper presents an exploratory study of factors for successful collaboration between industry and academia. A survey was designed for data collection and was firstly conducted in Sweden then replicated in Australia. The context for the two studies is different thus forming a starting point for potential generalizations in the future. From the two studies we conclude that the industrial side of collaboration is the key element for successful collaboration, with key factors being "Buy in and support from company management" and "Champion at company". Context-specific factors were also identified based on differences in the context between the two studies. These findings may help industry and academia to set up successful collaborative ventures.
Invalidation-based cache coherence protocols have been extensively studied in the context of large-scale shared-memory multiprocessors. Under a relaxed memory consistency model, most of the write latency can be hidden whereas cache misses still incur a severe performance problem. By contrast, update-based protocols have a potential to reduce both write and read penalties under relaxed memory consistency models because coherence misses can be completely eliminated. The purpose of this paper is to compare update-and invalidation-based protocols for their ability to reduce or hide memory access latencies and for their ease of implementation under relaxed memory consistency models. Based on a detailed simulation study, we find that write-update protocols augmented with simple competitive mechanisms-we call such protocols competitive-update protocols-can hide all the write latency and cut the read penalty by as much as 46% at the cost of some increase in the memory traffic. However, as compared to write-invalidate, update-based protocols require more aggressive memory consistency models and more local buffering in the second-level cache to be effective. In addition, their increased number of global writes may cause increased synchronization overhead in applications with high contention for critical sections.
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