Implementation and evaluation of update-based cache protocols under relaxed memory consistency models

Abstract

Invalidation-based cache coherence protocols have been extensively studied in the context of large-scale shared-memory multiprocessors. Under a relaxed memory consistency model, most of the write latency can be hidden whereas cache misses still incur a severe performance problem. By contrast, update-based protocols have a potential to reduce both write and read penalties under relaxed memory consistency models because coherence misses can be completely eliminated. The purpose of this paper is to compare update-and invalidation-based protocols for their ability to reduce or hide memory access latencies and for their ease of implementation under relaxed memory consistency models. Based on a detailed simulation study, we find that write-update protocols augmented with simple competitive mechanisms-we call such protocols competitive-update protocols-can hide all the write latency and cut the read penalty by as much as 46% at the cost of some increase in the memory traffic. However, as compared to write-invalidate, update-based protocols require more aggressive memory consistency models and more local buffering in the second-level cache to be effective. In addition, their increased number of global writes may cause increased synchronization overhead in applications with high contention for critical sections.

An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing

“…Although update protocols have the potential to eliminate remote misses by pre-pushing data to where it will soon be consumed, they have a tendency to generate excessive amounts of coherence traffic [7,15]. These extra coherence messages are typically due to sending updates to nodes that no longer are consuming the data.…”

A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures

“…The Archibald scheme [4] extends the write-once protocol by allowing a greater number of updates. The competitive scheme [5] is another example of such protocols. With this scheme, a counter is associated with each cache block is preset to a value called the Competitive threshold.…”

Boosting the performance of shared memory multiprocessors

“…Competitive updating is an example of such a protocol. We have taken this approach by associating a counter of log 2 n bits with each second-level cache line 4 (an approach similar to competitive snooping 12 ). We found in studying this protocol that for modest sizes of n (say 4), traffic goes down drastically.…”

“…4,5 In this optimization, the idea is to enhance basic write-update protocols to cut down update traffic, thus making the use of an update-based coherence policy (as opposed to a write-invalidate policy) feasible.…”